From 032ea9b2db870ad9b2a039f8c4020e38f5dd7f62 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Mon, 8 Jan 2007 18:18:28 -0500 Subject: the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in. src/arch/sparc/interrupts.hh: fill in how we do interrupts on sparc a little bit. 1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU. 2) fill in getInterrupts() a little bit. also, update the bitfield access to be HPSTATE::hpriv, etc. src/arch/sparc/ua2005.cc: 1) update formatting 2) change the way interrupts are done to use the new way to tickle the CPU. src/cpu/base.cc: src/cpu/base.hh: overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value. --HG-- extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5 --- src/cpu/base.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/cpu/base.cc') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 31604ad58..b03bc19a5 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -362,6 +362,12 @@ BaseCPU::ProfileEvent::process() schedule(curTick + interval); } +void +BaseCPU::post_interrupt(int int_type) +{ + interrupts.post(int_type); +} + void BaseCPU::post_interrupt(int int_num, int index) { -- cgit v1.2.3