From 5187a24d496cd16bfe440f52ff0c45ab0e185306 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 4 Apr 2018 16:27:04 +0100 Subject: sim,cpu,mem,arch: Introduced MasterInfo data structure With this patch a gem5 System will store more info about its Masters. While it was previously keeping track of the Master name and Master ID only, it is now adding a per-Master pointer to the SimObject related to the Master. This will make it possible for a client to query a System for a Master using either the master's name or the master's pointer. Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/9781 Reviewed-by: Jason Lowe-Power Maintainer: Nikos Nikoleris --- src/cpu/base.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/base.cc') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 4fd804b9c..c576f1def 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -127,8 +127,8 @@ CPUProgressEvent::description() const BaseCPU::BaseCPU(Params *p, bool is_checker) : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), - _instMasterId(p->system->getMasterId(name() + ".inst")), - _dataMasterId(p->system->getMasterId(name() + ".data")), + _instMasterId(p->system->getMasterId(this, "inst")), + _dataMasterId(p->system->getMasterId(this, "data")), _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid), _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), interrupts(p->interrupts), profileEvent(NULL), -- cgit v1.2.3