From 8aaa39e93dfe000ad423b585e78a4c2ee7418363 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sun, 12 Feb 2012 16:07:38 -0600 Subject: mem: Add a master ID to each request object. This change adds a master id to each request object which can be used identify every device in the system that is capable of issuing a request. This is part of the way to removing the numCpus+1 stats in the cache and replacing them with the master ids. This is one of a series of changes that make way for the stats output to be changed to python. --- src/cpu/base.hh | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/cpu/base.hh') diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 8250338cc..93e5476ef 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -104,6 +104,12 @@ class BaseCPU : public MemObject // therefore no setCpuId() method is provided int _cpuId; + /** instruction side request id that must be placed in all requests */ + MasterID _instMasterId; + + /** data side request id that must be placed in all requests */ + MasterID _dataMasterId; + /** * Define a base class for the CPU ports (instruction and data) * that is refined in the subclasses. This class handles the @@ -144,6 +150,11 @@ class BaseCPU : public MemObject /** Reads this CPU's ID. */ int cpuId() { return _cpuId; } + /** Reads this CPU's unique data requestor ID */ + MasterID dataMasterId() { return _dataMasterId; } + /** Reads this CPU's unique instruction requestor ID */ + MasterID instMasterId() { return _instMasterId; } + // Tick currentTick; inline Tick frequency() const { return SimClock::Frequency / clock; } inline Tick ticks(int numCycles) const { return clock * numCycles; } -- cgit v1.2.3