From ea11c7bdbefc8eb640f875cdf91a6d6bed398ec4 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Fri, 7 Jul 2006 15:15:11 -0400 Subject: Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory configs/test/test.py: Update to use new cpu getPort functionality src/cpu/base.cc: Make cpu's a memObject to expose getPort interface src/cpu/base.hh: Make cpu's a memObject to export getPort interface src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Now use the connector via getPort interface src/mem/cache/base_cache.cc: Make sure the cache recognizes all port names --HG-- extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61 --- src/cpu/base.hh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/cpu/base.hh') diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 5256a411f..2be6e4e81 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -37,15 +37,16 @@ #include "base/statistics.hh" #include "config/full_system.hh" #include "sim/eventq.hh" -#include "sim/sim_object.hh" +#include "mem/mem_object.hh" #include "arch/isa_traits.hh" class BranchPred; class CheckerCPU; class ThreadContext; class System; +class Port; -class BaseCPU : public SimObject +class BaseCPU : public MemObject { protected: // CPU's clock period in terms of the number of ticks of curTime. -- cgit v1.2.3