From 1926faac067c5ab01c0a925ccd5afc4d2bd6b83a Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Mon, 23 Oct 2006 14:00:07 -0400
Subject: Add in support for LL/SC in the O3 CPU.  Needs to be fully tested.

src/cpu/base_dyn_inst.hh:
    Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code).
src/cpu/base_dyn_inst_impl.hh:
    Add variable to track if the result of the instruction should be recorded.
src/cpu/o3/alpha/cpu_impl.hh:
    Clear lock flag upon hwrei.
src/cpu/o3/lsq_unit.hh:
    Use ISA specified handling of locked reads.
src/cpu/o3/lsq_unit_impl.hh:
    Use ISA specified handling of locked writes.

--HG--
extra : convert_revision : 1f5c789c35deb4b016573c02af4aab60d726c0e5
---
 src/cpu/base_dyn_inst.hh | 42 +++++++++++++++++++++++++++++++-----------
 1 file changed, 31 insertions(+), 11 deletions(-)

(limited to 'src/cpu/base_dyn_inst.hh')

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index c68810954..4a4555566 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -206,6 +206,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
      */
     Result instResult;
 
+    /** Records changes to result? */
+    bool recordResult;
+
     /** PC of this instruction. */
     Addr PC;
 
@@ -263,6 +266,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** Dumps out contents of this BaseDynInst into given string. */
     void dump(std::string &outstring);
 
+    /** Read this CPU's ID. */
+    int readCpuId() { return cpu->readCpuId(); }
+
     /** Returns the fault type. */
     Fault getFault() { return fault; }
 
@@ -402,37 +408,42 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** Records an integer register being set to a value. */
     void setIntReg(const StaticInst *si, int idx, uint64_t val)
     {
-        instResult.integer = val;
+        if (recordResult)
+            instResult.integer = val;
     }
 
     /** Records an fp register being set to a value. */
     void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
     {
-        if (width == 32)
-            instResult.dbl = (double)val;
-        else if (width == 64)
-            instResult.dbl = val;
-        else
-            panic("Unsupported width!");
+        if (recordResult) {
+            if (width == 32)
+                instResult.dbl = (double)val;
+            else if (width == 64)
+                instResult.dbl = val;
+            else
+                panic("Unsupported width!");
+        }
     }
 
     /** Records an fp register being set to a value. */
     void setFloatReg(const StaticInst *si, int idx, FloatReg val)
     {
-//        instResult.fp = val;
-        instResult.dbl = (double)val;
+        if (recordResult)
+            instResult.dbl = (double)val;
     }
 
     /** Records an fp register being set to an integer value. */
     void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
     {
-        instResult.integer = val;
+        if (recordResult)
+            instResult.integer = val;
     }
 
     /** Records an fp register being set to an integer value. */
     void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
     {
-        instResult.integer = val;
+        if (recordResult)
+            instResult.integer = val;
     }
 
     /** Records that one of the source registers is ready. */
@@ -624,6 +635,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
 
     /** Sets iterator for this instruction in the list of all insts. */
     void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
+
+  public:
+    /** Returns the number of consecutive store conditional failures. */
+    unsigned readStCondFailures()
+    { return thread->storeCondFailures; }
+
+    /** Sets the number of consecutive store conditional failures. */
+    void setStCondFailures(unsigned sc_failures)
+    { thread->storeCondFailures = sc_failures; }
 };
 
 template<class Impl>
-- 
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