From 8aaa39e93dfe000ad423b585e78a4c2ee7418363 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sun, 12 Feb 2012 16:07:38 -0600 Subject: mem: Add a master ID to each request object. This change adds a master id to each request object which can be used identify every device in the system that is capable of issuing a request. This is part of the way to removing the numCpus+1 stats in the cache and replacing them with the master ids. This is one of a series of changes that make way for the stats output to be changed to python. --- src/cpu/base_dyn_inst.hh | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/cpu/base_dyn_inst.hh') diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 027e3f573..882d5ba41 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -424,6 +424,9 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Read this CPU's ID. */ int cpuId() { return cpu->cpuId(); } + /** Read this CPU's data requestor ID */ + MasterID masterId() { return cpu->dataMasterId(); } + /** Read this context's system-wide ID **/ int contextId() { return thread->contextId(); } @@ -878,7 +881,7 @@ BaseDynInst::readMem(Addr addr, uint8_t *data, sreqLow = savedSreqLow; sreqHigh = savedSreqHigh; } else { - req = new Request(asid, addr, size, flags, this->pc.instAddr(), + req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), thread->contextId(), threadNumber); // Only split the request if the ISA supports unaligned accesses. @@ -940,7 +943,7 @@ BaseDynInst::writeMem(uint8_t *data, unsigned size, sreqLow = savedSreqLow; sreqHigh = savedSreqHigh; } else { - req = new Request(asid, addr, size, flags, this->pc.instAddr(), + req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), thread->contextId(), threadNumber); // Only split the request if the ISA supports unaligned accesses. -- cgit v1.2.3