From 93da9eb7f6d9b2ca84de74afd3e0cb07188db9e6 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 22 Oct 2007 14:30:45 -0700
Subject: CPU: Add functions to the "ExecContext"s that translate a given
 address.

--HG--
extra : convert_revision : 7d898c6b6b13094fd05326eaa0b095a3ab132397
---
 src/cpu/base_dyn_inst.hh | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

(limited to 'src/cpu/base_dyn_inst.hh')

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 0f2a90bf6..74b250207 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -102,6 +102,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
     template <class T>
     Fault read(Addr addr, T &data, unsigned flags);
 
+    Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
+            int size, unsigned flags);
+
     /**
      * Does a write to a given address.
      * @param data The data to be written.
@@ -114,6 +117,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
     Fault write(T data, Addr addr, unsigned flags,
                         uint64_t *res);
 
+    Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
+            int size, unsigned flags);
+
     void prefetch(Addr addr, unsigned flags);
     void writeHint(Addr addr, int size, unsigned flags);
     Fault copySrcTranslate(Addr src);
@@ -837,6 +843,29 @@ class BaseDynInst : public FastAlloc, public RefCounted
     { thread->storeCondFailures = sc_failures; }
 };
 
+template<class Impl>
+Fault
+BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr,
+        int size, unsigned flags)
+{
+    if (traceData) {
+        traceData->setAddr(vaddr);
+    }
+
+    reqMade = true;
+    Request *req = new Request();
+    req->setVirt(asid, vaddr, size, flags, PC);
+    req->setThreadContext(thread->readCpuId(), threadNumber);
+
+    fault = cpu->translateDataReadReq(req, thread);
+
+    if (fault == NoFault)
+        paddr = req->getPaddr();
+
+    delete req;
+    return fault;
+}
+
 template<class Impl>
 template<class T>
 inline Fault
@@ -888,6 +917,29 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
     return fault;
 }
 
+template<class Impl>
+Fault
+BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
+        int size, unsigned flags)
+{
+    if (traceData) {
+        traceData->setAddr(vaddr);
+    }
+
+    reqMade = true;
+    Request *req = new Request();
+    req->setVirt(asid, vaddr, size, flags, PC);
+    req->setThreadContext(thread->readCpuId(), threadNumber);
+
+    fault = cpu->translateDataWriteReq(req, thread);
+
+    if (fault == NoFault)
+        paddr = req->getPaddr();
+
+    delete req;
+    return fault;
+}
+
 template<class Impl>
 template<class T>
 inline Fault
-- 
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