From a1aba01a02a8c1261120de83d8fbfd6624f0cb17 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Feb 2009 10:15:34 -0800
Subject: CPU: Get rid of translate... functions from various interface
 classes.

---
 src/cpu/base_dyn_inst.hh | 56 ++----------------------------------------------
 1 file changed, 2 insertions(+), 54 deletions(-)

(limited to 'src/cpu/base_dyn_inst.hh')

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index f40616e54..f58bf7cf8 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -115,9 +115,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
     template <class T>
     Fault read(Addr addr, T &data, unsigned flags);
 
-    Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-
     /**
      * Does a write to a given address.
      * @param data The data to be written.
@@ -130,9 +127,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
     Fault write(T data, Addr addr, unsigned flags,
                         uint64_t *res);
 
-    Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-
     void prefetch(Addr addr, unsigned flags);
     void writeHint(Addr addr, int size, unsigned flags);
     Fault copySrcTranslate(Addr src);
@@ -856,29 +850,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
     { thread->storeCondFailures = sc_failures; }
 };
 
-template<class Impl>
-Fault
-BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr,
-        int size, unsigned flags)
-{
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    reqMade = true;
-    Request *req = new Request();
-    req->setVirt(asid, vaddr, size, flags, PC);
-    req->setThreadContext(thread->contextId(), threadNumber);
-
-    fault = cpu->translateDataReadReq(req, thread);
-
-    if (fault == NoFault)
-        paddr = req->getPaddr();
-
-    delete req;
-    return fault;
-}
-
 template<class Impl>
 template<class T>
 inline Fault
@@ -889,7 +860,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
     req->setThreadContext(thread->contextId(), threadNumber);
 
-    fault = cpu->translateDataReadReq(req, thread);
+    fault = cpu->dtb->translate(req, thread->getTC(), false);
 
     if (req->isUncacheable())
         isUncacheable = true;
@@ -930,29 +901,6 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
     return fault;
 }
 
-template<class Impl>
-Fault
-BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
-        int size, unsigned flags)
-{
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    reqMade = true;
-    Request *req = new Request();
-    req->setVirt(asid, vaddr, size, flags, PC);
-    req->setThreadContext(thread->contextId(), threadNumber);
-
-    fault = cpu->translateDataWriteReq(req, thread);
-
-    if (fault == NoFault)
-        paddr = req->getPaddr();
-
-    delete req;
-    return fault;
-}
-
 template<class Impl>
 template<class T>
 inline Fault
@@ -968,7 +916,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
     req->setThreadContext(thread->contextId(), threadNumber);
 
-    fault = cpu->translateDataWriteReq(req, thread);
+    fault = cpu->dtb->translate(req, thread->getTC(), true);
 
     if (req->isUncacheable())
         isUncacheable = true;
-- 
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