From cf79dba504e2ed47ea82dae6cfc71662d1bc25a0 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Thu, 8 Jun 2006 16:58:50 -0400
Subject: Get O3 CPU mostly working in full system, and fix an FP bug that
 showed up.

It still does not yet handle retries.

src/cpu/base_dyn_inst.hh:
    Get working in full-system mode and fix some FP bugs.
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/thread_context.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/thread_state.hh:
    Get working in full system.
src/cpu/checker/o3_cpu_builder.cc:
    Checker does not take a MemObject as a simobj parameter.
src/cpu/o3/alpha_dyn_inst.hh:
    Fix up float regs.
src/cpu/o3/regfile.hh:
    Fix up an fp error, print out more useful output messages.

--HG--
extra : convert_revision : d7cc152a051c697f18b7ee9e14050fbf3ffa5966
---
 src/cpu/base_dyn_inst.hh | 30 +++++++++++++++++++++---------
 1 file changed, 21 insertions(+), 9 deletions(-)

(limited to 'src/cpu/base_dyn_inst.hh')

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index e69e00d6c..263a24521 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -73,8 +73,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
     typedef TheISA::ExtMachInst ExtMachInst;
     // Logical register index type.
     typedef TheISA::RegIndex RegIndex;
-    // Integer register index type.
+    // Integer register type.
     typedef TheISA::IntReg IntReg;
+    // Floating point register type.
+    typedef TheISA::FloatReg FloatReg;
 
     // The DynInstPtr type.
     typedef typename Impl::DynInstPtr DynInstPtr;
@@ -442,17 +444,27 @@ class BaseDynInst : public FastAlloc, public RefCounted
         instResult.integer = val;
     }
 
-    void setFloatRegSingle(const StaticInst *si, int idx, float val)
+    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+    {
+        if (width == 32)
+            instResult.fp = val;
+        else if (width == 64)
+            instResult.dbl = val;
+        else
+            panic("Unsupported width!");
+    }
+
+    void setFloatReg(const StaticInst *si, int idx, FloatReg val)
     {
         instResult.fp = val;
     }
 
-    void setFloatRegDouble(const StaticInst *si, int idx, double val)
+    void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
     {
-        instResult.dbl = val;
+        instResult.integer = val;
     }
 
-    void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
+    void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
     {
         instResult.integer = val;
     }
@@ -657,14 +669,14 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
         return TheISA::genAlignmentFault();
     }
 
-    fault = cpu->translateDataReadReq(req);
+    fault = cpu->translateDataReadReq(req, thread);
 
     if (fault == NoFault) {
         effAddr = req->getVaddr();
         physEffAddr = req->getPaddr();
         memReqFlags = req->getFlags();
 
-#if FULL_SYSTEM
+#if 0
         if (cpu->system->memctrl->badaddr(physEffAddr)) {
             fault = TheISA::genMachineCheckFault();
             data = (T)-1;
@@ -712,13 +724,13 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
         return TheISA::genAlignmentFault();
     }
 
-    fault = cpu->translateDataWriteReq(req);
+    fault = cpu->translateDataWriteReq(req, thread);
 
     if (fault == NoFault) {
         effAddr = req->getVaddr();
         physEffAddr = req->getPaddr();
         memReqFlags = req->getFlags();
-#if FULL_SYSTEM
+#if 0
         if (cpu->system->memctrl->badaddr(physEffAddr)) {
             fault = TheISA::genMachineCheckFault();
         } else {
-- 
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