From 3bb5fd8c44bbac6cbcfd18aed5fd46c112d19d7f Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 8 Apr 2007 01:42:42 +0000
Subject: Get the "hard" SPARC instructions working in o3. I don't like that
 the IsStoreConditional flag needs to be set for them because they aren't
 store conditional instructions, and I should fix the format code which is not
 handling the opt_flags correctly.

--HG--
extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
---
 src/cpu/base_dyn_inst.hh | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/cpu/base_dyn_inst.hh')

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 6c6d90076..eed05c2f1 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -877,6 +877,11 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
         effAddrValid = true;
         physEffAddr = req->getPaddr();
         memReqFlags = req->getFlags();
+
+        if (req->isCondSwap()) {
+            assert(res);
+            req->setExtraData(*res);
+        }
 #if 0
         if (cpu->system->memctrl->badaddr(physEffAddr)) {
             fault = TheISA::genMachineCheckFault();
-- 
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