From f54020eb8155371725ab75b0fc5c419287eca084 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 4 Jun 2018 09:40:19 +0100
Subject: misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
---
 src/cpu/checker/cpu.cc | 49 ++++++++++++++++++++-----------------------------
 1 file changed, 20 insertions(+), 29 deletions(-)

(limited to 'src/cpu/checker/cpu.cc')

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 1533d7405..8329e3191 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -69,7 +69,6 @@ CheckerCPU::CheckerCPU(Params *p)
     : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
       tc(NULL), thread(NULL)
 {
-    memReq = NULL;
     curStaticInst = NULL;
     curMacroStaticInst = NULL;
 
@@ -156,27 +155,28 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
 
     // Need to account for multiple accesses like the Atomic and TimingSimple
     while (1) {
-        memReq = new Request(0, addr, size, flags, masterId,
-                             thread->pcState().instAddr(), tc->contextId());
+        auto mem_req = std::make_shared<Request>(
+            0, addr, size, flags, masterId,
+            thread->pcState().instAddr(), tc->contextId());
 
         // translate to physical address
-        fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
+        fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read);
 
         if (!checked_flags && fault == NoFault && unverifiedReq) {
-            flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
-                                     memReq->getPaddr(), memReq->getFlags());
-            pAddr = memReq->getPaddr();
+            flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
+                                     mem_req->getPaddr(), mem_req->getFlags());
+            pAddr = mem_req->getPaddr();
             checked_flags = true;
         }
 
         // Now do the access
         if (fault == NoFault &&
-            !memReq->getFlags().isSet(Request::NO_ACCESS)) {
-            PacketPtr pkt = Packet::createRead(memReq);
+            !mem_req->getFlags().isSet(Request::NO_ACCESS)) {
+            PacketPtr pkt = Packet::createRead(mem_req);
 
             pkt->dataStatic(data);
 
-            if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
+            if (!(mem_req->isUncacheable() || mem_req->isMmappedIpr())) {
                 // Access memory to see if we have the same data
                 dcachePort->sendFunctional(pkt);
             } else {
@@ -184,24 +184,16 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
                 memcpy(data, unverifiedMemData, size);
             }
 
-            delete memReq;
-            memReq = NULL;
             delete pkt;
         }
 
         if (fault != NoFault) {
-            if (memReq->isPrefetch()) {
+            if (mem_req->isPrefetch()) {
                 fault = NoFault;
             }
-            delete memReq;
-            memReq = NULL;
             break;
         }
 
-        if (memReq != NULL) {
-            delete memReq;
-        }
-
         //If we don't need to access a second cache line, stop now.
         if (secondAddr <= addr)
         {
@@ -244,16 +236,17 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
 
     // Need to account for a multiple access like Atomic and Timing CPUs
     while (1) {
-        memReq = new Request(0, addr, size, flags, masterId,
-                             thread->pcState().instAddr(), tc->contextId());
+        auto mem_req = std::make_shared<Request>(
+            0, addr, size, flags, masterId,
+            thread->pcState().instAddr(), tc->contextId());
 
         // translate to physical address
-        fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
+        fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
 
         if (!checked_flags && fault == NoFault && unverifiedReq) {
-           flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
-                                    memReq->getPaddr(), memReq->getFlags());
-           pAddr = memReq->getPaddr();
+           flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
+                                    mem_req->getPaddr(), mem_req->getFlags());
+           pAddr = mem_req->getPaddr();
            checked_flags = true;
         }
 
@@ -264,9 +257,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
          * enabled.  This is left as future work for the Checker: LSQ snooping
          * and memory validation after stores have committed.
          */
-        bool was_prefetch = memReq->isPrefetch();
-
-        delete memReq;
+        bool was_prefetch = mem_req->isPrefetch();
 
         //If we don't need to access a second cache line, stop now.
         if (fault != NoFault || secondAddr <= addr)
@@ -337,7 +328,7 @@ CheckerCPU::dbg_vtophys(Addr addr)
  * Checks if the flags set by the Checker and Checkee match.
  */
 bool
-CheckerCPU::checkFlags(RequestPtr unverified_req, Addr vAddr,
+CheckerCPU::checkFlags(const RequestPtr &unverified_req, Addr vAddr,
                        Addr pAddr, int flags)
 {
     Addr unverifiedVAddr = unverified_req->getVaddr();
-- 
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