From 00da08902918da13fccc3f2266b7b2f5d0080708 Mon Sep 17 00:00:00 2001 From: Rekai Gonzalez-Alberquilla Date: Wed, 5 Apr 2017 13:24:00 -0500 Subject: cpu: Added interface for vector reg file This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/2705 --- src/cpu/checker/cpu.hh | 138 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) (limited to 'src/cpu/checker/cpu.hh') diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 6571d034a..213106bd2 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -96,6 +96,7 @@ class CheckerCPU : public BaseCPU, public ExecContext typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::MiscReg MiscReg; + using VecRegContainer = TheISA::VecRegContainer; /** id attached to all issued requests */ MasterID masterId; @@ -225,6 +226,111 @@ class CheckerCPU : public BaseCPU, public ExecContext return thread->readFloatRegBits(reg.index()); } + /** + * Read source vector register operand. + */ + const VecRegContainer& readVecRegOperand(const StaticInst *si, + int idx) const override + { + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isVecReg()); + return thread->readVecReg(reg); + } + + /** + * Read destination vector register operand for modification. + */ + VecRegContainer& getWritableVecRegOperand(const StaticInst *si, + int idx) override + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecReg()); + return thread->getWritableVecReg(reg); + } + + /** Vector Register Lane Interfaces. */ + /** @{ */ + /** Reads source vector 8bit operand. */ + virtual ConstVecLane8 + readVec8BitLaneOperand(const StaticInst *si, int idx) const + override + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecReg()); + return thread->readVec8BitLaneReg(reg); + } + + /** Reads source vector 16bit operand. */ + virtual ConstVecLane16 + readVec16BitLaneOperand(const StaticInst *si, int idx) const + override + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecReg()); + return thread->readVec16BitLaneReg(reg); + } + + /** Reads source vector 32bit operand. */ + virtual ConstVecLane32 + readVec32BitLaneOperand(const StaticInst *si, int idx) const + override + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecReg()); + return thread->readVec32BitLaneReg(reg); + } + + /** Reads source vector 64bit operand. */ + virtual ConstVecLane64 + readVec64BitLaneOperand(const StaticInst *si, int idx) const + override + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecReg()); + return thread->readVec64BitLaneReg(reg); + } + + /** Write a lane of the destination vector operand. */ + template + void + setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecReg()); + return thread->setVecLane(reg, val); + } + virtual void + setVecLaneOperand(const StaticInst *si, int idx, + const LaneData& val) override + { + setVecLaneOperandT(si, idx, val); + } + virtual void + setVecLaneOperand(const StaticInst *si, int idx, + const LaneData& val) override + { + setVecLaneOperandT(si, idx, val); + } + virtual void + setVecLaneOperand(const StaticInst *si, int idx, + const LaneData& val) override + { + setVecLaneOperandT(si, idx, val); + } + virtual void + setVecLaneOperand(const StaticInst *si, int idx, + const LaneData& val) override + { + setVecLaneOperandT(si, idx, val); + } + /** @} */ + + VecElem readVecElemOperand(const StaticInst *si, int idx) const override + { + const RegId& reg = si->srcRegIdx(idx); + return thread->readVecElem(reg); + } + CCReg readCCRegOperand(const StaticInst *si, int idx) override { const RegId& reg = si->srcRegIdx(idx); @@ -239,6 +345,20 @@ class CheckerCPU : public BaseCPU, public ExecContext InstResult::ResultType::Scalar)); } + template + void setVecResult(T&& t) + { + result.push(InstResult(std::forward(t), + InstResult::ResultType::VecReg)); + } + + template + void setVecElemResult(T&& t) + { + result.push(InstResult(std::forward(t), + InstResult::ResultType::VecElem)); + } + void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override { @@ -274,6 +394,24 @@ class CheckerCPU : public BaseCPU, public ExecContext setScalarResult((uint64_t)val); } + void setVecRegOperand(const StaticInst *si, int idx, + const VecRegContainer& val) override + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecReg()); + thread->setVecReg(reg, val); + setVecResult(val); + } + + void setVecElemOperand(const StaticInst *si, int idx, + const VecElem val) override + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecElem()); + thread->setVecElem(reg, val); + setVecElemResult(val); + } + bool readPredicate() override { return thread->readPredicate(); } void setPredicate(bool val) override { -- cgit v1.2.3