From cdacbe734a9e6e0f20e0a37ef694995373b83f66 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 8 Nov 2010 13:58:22 -0600 Subject: ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. This change modifies the way prefetches work. They are now like normal loads that don't writeback a register. Previously prefetches were supposed to call prefetch() on the exection context, so they executed with execute() methods instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs are blank, meaning that they get executed, but don't actually do anything. On Alpha dead cache copy code was removed and prefetches are now normal ops. They count as executed operations, but still don't do anything and IsMemRef is not longer set on them. On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch instructions. The timing simple CPU doesn't try to do anything special for prefetches now and they execute with the normal memory code path. --- src/cpu/checker/cpu.hh | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'src/cpu/checker/cpu.hh') diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index df5d8209b..efd8a4776 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -178,20 +178,6 @@ class CheckerCPU : public BaseCPU void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } - void prefetch(Addr addr, unsigned flags) - { - // need to do this... - } - - void writeHint(Addr addr, int size, unsigned flags) - { - // need to do this... - } - - Fault copySrcTranslate(Addr src); - - Fault copy(Addr dest); - // The register accessor methods provide the index of the // instruction's operand (e.g., 0 or 1), not the architectural // register index, to simplify the implementation of register -- cgit v1.2.3