From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sun, 26 Jul 2015 10:21:20 -0500
Subject: cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.
---
 src/cpu/checker/cpu_impl.hh | 74 +++++++++++++++++++++++++++++++--------------
 1 file changed, 52 insertions(+), 22 deletions(-)

(limited to 'src/cpu/checker/cpu_impl.hh')

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 289861521..d6a467358 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -491,7 +491,9 @@ Checker<Impl>::validateExecution(DynInstPtr &inst)
         // Unverifiable instructions assume they were executed
         // properly by the CPU. Grab the result from the
         // instruction and write it to the register.
-        copyResult(inst, 0, idx);
+        Result r;
+        r.integer = 0;
+        copyResult(inst, r, idx);
     } else if (inst->numDestRegs() > 0 && !result.empty()) {
         DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
                          inst->numDestRegs(), result.size());
@@ -525,7 +527,9 @@ Checker<Impl>::validateExecution(DynInstPtr &inst)
         // The load/store queue in Detailed CPU can also cause problems
         // if load/store forwarding is allowed.
         if (inst->isLoad() && warnOnlyOnLoadError) {
-            copyResult(inst, inst_val, idx);
+            Result r;
+            r.integer = inst_val;
+            copyResult(inst, r, idx);
         } else {
             handleError(inst);
         }
@@ -590,7 +594,7 @@ Checker<Impl>::validateState()
 
 template <class Impl>
 void
-Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
+Checker<Impl>::copyResult(DynInstPtr &inst, Result mismatch_val,
                           int start_idx)
 {
     // We've already popped one dest off the queue,
@@ -599,39 +603,65 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
         RegIndex idx = inst->destRegIdx(start_idx);
         switch (regIdxToClass(idx)) {
           case IntRegClass:
-            thread->setIntReg(idx, mismatch_val);
+            thread->setIntReg(idx, mismatch_val.integer);
             break;
           case FloatRegClass:
-            thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, mismatch_val);
+            thread->setFloatRegBits(idx - TheISA::FP_Reg_Base,
+                    mismatch_val.integer);
             break;
           case CCRegClass:
-            thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val);
+            thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val.integer);
+            break;
+          case VectorRegClass:
+            thread->setVectorReg(idx - TheISA::Vector_Reg_Base,
+                    mismatch_val.vector);
             break;
           case MiscRegClass:
             thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
-                               mismatch_val);
+                               mismatch_val.integer);
             break;
         }
     }
+
     start_idx++;
-    uint64_t res = 0;
     for (int i = start_idx; i < inst->numDestRegs(); i++) {
         RegIndex idx = inst->destRegIdx(i);
-        inst->template popResult<uint64_t>(res);
         switch (regIdxToClass(idx)) {
-          case IntRegClass:
-            thread->setIntReg(idx, res);
-            break;
-          case FloatRegClass:
-            thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res);
-            break;
-          case CCRegClass:
-            thread->setCCReg(idx - TheISA::CC_Reg_Base, res);
-            break;
-          case MiscRegClass:
-            // Try to get the proper misc register index for ARM here...
-            thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
-            break;
+          case IntRegClass: {
+              uint64_t res = 0;
+              inst->template popResult<uint64_t>(res);
+              thread->setIntReg(idx, res);
+          }
+          break;
+
+          case FloatRegClass: {
+              uint64_t res = 0;
+              inst->template popResult<uint64_t>(res);
+              thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res);
+          }
+          break;
+
+          case CCRegClass: {
+              uint64_t res = 0;
+              inst->template popResult<uint64_t>(res);
+              thread->setCCReg(idx - TheISA::CC_Reg_Base, res);
+          }
+          break;
+
+          case VectorRegClass: {
+              VectorReg res;
+              inst->template popResult<VectorReg>(res);
+              thread->setVectorReg(idx - TheISA::Vector_Reg_Base, res);
+          }
+          break;
+
+          case MiscRegClass: {
+              // Try to get the proper misc register index for ARM here...
+              uint64_t res = 0;
+              inst->template popResult<uint64_t>(res);
+              thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
+          }
+          break;
             // else Register is out of range...
         }
     }
-- 
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