From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001
From: Yasuko Eckert <yasuko.eckert@amd.com>
Date: Tue, 15 Oct 2013 14:22:44 -0400
Subject: cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
---
 src/cpu/checker/cpu.hh            | 14 ++++++++++++++
 src/cpu/checker/cpu_impl.hh       |  6 ++++++
 src/cpu/checker/thread_context.hh | 17 +++++++++++++++++
 3 files changed, 37 insertions(+)

(limited to 'src/cpu/checker')

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 637481706..c49f264f9 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -223,6 +224,12 @@ class CheckerCPU : public BaseCPU
         return thread->readFloatRegBits(reg_idx);
     }
 
+    uint64_t readCCRegOperand(const StaticInst *si, int idx)
+    {
+        int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
+        return thread->readCCReg(reg_idx);
+    }
+
     template <class T>
     void setResult(T t)
     {
@@ -252,6 +259,13 @@ class CheckerCPU : public BaseCPU
         setResult<uint64_t>(val);
     }
 
+    void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
+    {
+        int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
+        thread->setCCReg(reg_idx, val);
+        setResult<uint64_t>(val);
+    }
+
     bool readPredicate() { return thread->readPredicate(); }
     void setPredicate(bool val)
     {
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 185fed88e..e18644e0e 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -606,6 +606,9 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
           case FloatRegClass:
             thread->setFloatRegBits(idx, mismatch_val);
             break;
+          case CCRegClass:
+            thread->setCCReg(idx, mismatch_val);
+            break;
           case MiscRegClass:
             thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
                                mismatch_val);
@@ -624,6 +627,9 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
           case FloatRegClass:
             thread->setFloatRegBits(idx, res);
             break;
+          case CCRegClass:
+            thread->setCCReg(idx, res);
+            break;
           case MiscRegClass:
             // Try to get the proper misc register index for ARM here...
             thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 80726ff19..c06e03fc6 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -216,6 +217,9 @@ class CheckerThreadContext : public ThreadContext
     FloatRegBits readFloatRegBits(int reg_idx)
     { return actualTC->readFloatRegBits(reg_idx); }
 
+    CCReg readCCReg(int reg_idx)
+    { return actualTC->readCCReg(reg_idx); }
+
     void setIntReg(int reg_idx, uint64_t val)
     {
         actualTC->setIntReg(reg_idx, val);
@@ -234,6 +238,12 @@ class CheckerThreadContext : public ThreadContext
         checkerTC->setFloatRegBits(reg_idx, val);
     }
 
+    void setCCReg(int reg_idx, CCReg val)
+    {
+        actualTC->setCCReg(reg_idx, val);
+        checkerTC->setCCReg(reg_idx, val);
+    }
+
     /** Reads this thread's PC state. */
     TheISA::PCState pcState()
     { return actualTC->pcState(); }
@@ -289,6 +299,7 @@ class CheckerThreadContext : public ThreadContext
 
     int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
     int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
+    int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
 
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }
@@ -320,6 +331,12 @@ class CheckerThreadContext : public ThreadContext
 
     void setFloatRegBitsFlat(int idx, FloatRegBits val)
     { actualTC->setFloatRegBitsFlat(idx, val); }
+
+    CCReg readCCRegFlat(int idx)
+    { return actualTC->readCCRegFlat(idx); }
+
+    void setCCRegFlat(int idx, CCReg val)
+    { actualTC->setCCRegFlat(idx, val); }
 };
 
 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
-- 
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