From 7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 8 Apr 2009 22:21:27 -0700
Subject: tlb: Don't separate the TLB classes into an instruction TLB and a
 data TLB

---
 src/cpu/checker/cpu.hh            | 7 +++----
 src/cpu/checker/thread_context.hh | 4 ++--
 2 files changed, 5 insertions(+), 6 deletions(-)

(limited to 'src/cpu/checker')

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 0d3dddded..3b378700e 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -49,8 +49,7 @@
 #if FULL_SYSTEM
 namespace TheISA
 {
-    class ITB;
-    class DTB;
+    class TLB;
 }
 class Processor;
 class PhysicalMemory;
@@ -130,8 +129,8 @@ class CheckerCPU : public BaseCPU
 
     ThreadContext *tc;
 
-    TheISA::ITB *itb;
-    TheISA::DTB *dtb;
+    TheISA::TLB *itb;
+    TheISA::TLB *dtb;
 
 #if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 3c87f841f..6b21bf670 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -84,9 +84,9 @@ class CheckerThreadContext : public ThreadContext
 
     int cpuId() { return actualTC->cpuId(); }
 
-    TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
+    TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
 
-    TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
+    TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
 #if FULL_SYSTEM
     System *getSystemPtr() { return actualTC->getSystemPtr(); }
-- 
cgit v1.2.3