From 8aaa39e93dfe000ad423b585e78a4c2ee7418363 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sun, 12 Feb 2012 16:07:38 -0600 Subject: mem: Add a master ID to each request object. This change adds a master id to each request object which can be used identify every device in the system that is capable of issuing a request. This is part of the way to removing the numCpus+1 stats in the cache and replacing them with the master ids. This is one of a series of changes that make way for the stats output to be changed to python. --- src/cpu/checker/cpu.cc | 3 ++- src/cpu/checker/cpu.hh | 3 +++ src/cpu/checker/cpu_impl.hh | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) (limited to 'src/cpu/checker') diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index 372d00c6f..fb381d24d 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -60,6 +60,7 @@ using namespace TheISA; void CheckerCPU::init() { + masterId = systemPtr->getMasterId(name()); } CheckerCPU::CheckerCPU(Params *p) @@ -241,7 +242,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size, // Need to account for a multiple access like Atomic and Timing CPUs while (1) { memReq = new Request(); - memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr()); + memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr()); // translate to physical address fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write); diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 6f5125625..54e446932 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -93,6 +93,9 @@ class CheckerCPU : public BaseCPU typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::MiscReg MiscReg; + + /** id attached to all issued requests */ + MasterID masterId; public: virtual void init(); diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 7a99feb06..5688ee674 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -247,7 +247,7 @@ Checker::verify(DynInstPtr &completed_inst) fetch_PC, thread->contextId(), unverifiedInst->threadNumber); memReq->setVirt(0, fetch_PC, sizeof(MachInst), - Request::INST_FETCH, thread->instAddr()); + Request::INST_FETCH, masterId, thread->instAddr()); fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute); -- cgit v1.2.3