From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sun, 26 Jul 2015 10:21:20 -0500
Subject: cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.
---
 src/cpu/exec_context.hh | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

(limited to 'src/cpu/exec_context.hh')

diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index c65841db2..5c6b3fad7 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -76,6 +76,7 @@ class ExecContext {
     typedef TheISA::MiscReg MiscReg;
 
     typedef TheISA::CCReg CCReg;
+    typedef TheISA::VectorReg VectorReg;
 
   public:
     /**
@@ -126,6 +127,22 @@ class ExecContext {
     virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
     /** @} */
 
+    /**
+     * @{
+     * @name Vector Register Interfaces
+     *
+     */
+
+    /** Reads a vector register. */
+    virtual const VectorReg &readVectorRegOperand (const StaticInst *si,
+                                                   int idx) = 0;
+
+    /** Sets a vector register to a value. */
+    virtual void setVectorRegOperand(const StaticInst *si,
+                                     int idx, const VectorReg &val) = 0;
+
+    /** @} */
+
     /**
      * @{
      * @name Misc Register Interfaces
-- 
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