From 5e9d8795f2a2642843cbb73b2637adb97935521d Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 19 Dec 2006 02:11:33 -0500 Subject: fix twinx loads a little bit bugfixes and demap implementation in tlb ignore some more differencs for one cycle src/arch/sparc/isa/formats/mem/blockmem.isa: twinx has 2 micro-ops src/arch/sparc/isa/formats/mem/util.isa: fix the fault check for twinx src/arch/sparc/tlb.cc: tlb bugfixes and write demapping code src/cpu/exetrace.cc: don't halt on a couple more instruction (ldx, stx) when things differ beacuse of the way tlb faults are handled in legion. --HG-- extra : convert_revision : 1e156dead6ebd58b257213625ed63c3793ef4b71 --- src/cpu/exetrace.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/cpu/exetrace.cc') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 3fe40b4c1..dc76ae189 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -401,7 +401,11 @@ Trace::InstRecord::dump(ostream &outs) diffCcr || diffTl || diffGl || diffAsi || diffPil || diffCwp || diffCansave || diffCanrestore || diffOtherwin || diffCleanwin) - && !((staticInst->machInst & 0xC1F80000) == 0x81D00000)) { + && !((staticInst->machInst & 0xC1F80000) == 0x81D00000) + && !((staticInst->machInst & 0xC1F80000) == 0xC0580000) + && !((staticInst->machInst & 0xC1F80000) == 0xC0000000) + && !((staticInst->machInst & 0xC1F80000) == 0xC0700000)) { + outs << "Differences found between M5 and Legion:"; if (diffPC) outs << " [PC]"; -- cgit v1.2.3