From 0e96798fe0a56936f8590dbd301f2b07a1850e22 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Sun, 31 Jan 2010 18:25:13 -0500
Subject: configs/inorder: add options for switch-on-miss to inorder cpu

---
 src/cpu/inorder/InOrderCPU.py | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/cpu/inorder/InOrderCPU.py')

diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index a0b0466a7..d6db346d4 100644
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -30,10 +30,15 @@ from m5.params import *
 from m5.proxy import *
 from BaseCPU import BaseCPU
 
+class ThreadModel(Enum):
+    vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
+
 class InOrderCPU(BaseCPU):
     type = 'InOrderCPU'
     activity = Param.Unsigned(0, "Initial count")
 
+    threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
+    
     cachePorts = Param.Unsigned(2, "Cache Ports")
     stageWidth = Param.Unsigned(1, "Stage width")
 
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