From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001 From: Yasuko Eckert Date: Tue, 15 Oct 2013 14:22:44 -0400 Subject: cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. --- src/cpu/inorder/cpu.hh | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/cpu/inorder/cpu.hh') diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index d5a31cca8..1183f6fc9 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -93,6 +93,7 @@ class InOrderCPU : public BaseCPU typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; + typedef TheISA::CCReg CCReg; typedef TheISA::MiscReg MiscReg; typedef TheISA::RegIndex RegIndex; @@ -327,6 +328,9 @@ class InOrderCPU : public BaseCPU FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; } floatRegs; TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs]; +#ifdef ISA_HAS_CC_REGS + TheISA::CCReg ccRegs[ThePipeline::MaxThreads][TheISA::NumCCRegs]; +#endif /** ISA state */ std::vector isa; @@ -590,12 +594,16 @@ class InOrderCPU : public BaseCPU FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid); + CCReg readCCReg(RegIndex reg_idx, ThreadID tid); + void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid); void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid); void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid); + void setCCReg(RegIndex reg_idx, CCReg val, ThreadID tid); + RegIndex flattenRegIdx(RegIndex reg_idx, RegClass ®_type, ThreadID tid); /** Reads a miscellaneous register. */ -- cgit v1.2.3