From 561c33f0824a705cb360ecb4ae3bf8cfd490f007 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Sun, 19 Jun 2011 21:43:40 -0400 Subject: inorder: dont handle multiple faults on same cycle if a faulting instruction reaches an execution unit, then ignore it and pass it through the pipeline. Once we recognize the fault in the graduation unit, dont allow a second fault to creep in on the same cycle. --- src/cpu/inorder/cpu.hh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/cpu/inorder/cpu.hh') diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 8a0f2167b..a1e92f302 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -319,6 +319,7 @@ class InOrderCPU : public BaseCPU SkedCacheIt endOfSkedIt; ThePipeline::RSkedPtr frontEndSked; + ThePipeline::RSkedPtr faultSked; /** Add a new instruction schedule to the schedule cache */ void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked) @@ -366,6 +367,7 @@ class InOrderCPU : public BaseCPU } ThePipeline::RSkedPtr createFrontEndSked(); + ThePipeline::RSkedPtr createFaultSked(); ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst); class StageScheduler { @@ -751,7 +753,7 @@ class InOrderCPU : public BaseCPU virtual void wakeup(); #endif - // LL/SC debug functionality + /* LL/SC debug functionality unsigned stCondFails; unsigned readStCondFailures() @@ -759,6 +761,7 @@ class InOrderCPU : public BaseCPU unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; } + */ /** Returns a pointer to a thread context. */ ThreadContext *tcBase(ThreadID tid = 0) -- cgit v1.2.3