From f69b018571a6396d0e679d4d0eceb47ef4496530 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Wed, 4 Mar 2009 13:17:07 -0500 Subject: make handling of interstage buffers (i.e. StageQueues) more consistent: (1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to get StageQueue size for all threads --- src/cpu/inorder/pipeline_stage.hh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/cpu/inorder/pipeline_stage.hh') diff --git a/src/cpu/inorder/pipeline_stage.hh b/src/cpu/inorder/pipeline_stage.hh index 833547704..17ca32595 100644 --- a/src/cpu/inorder/pipeline_stage.hh +++ b/src/cpu/inorder/pipeline_stage.hh @@ -184,7 +184,7 @@ class PipelineStage virtual bool processInstSchedule(DynInstPtr inst); /** Is there room in the next stage buffer for this instruction? */ - virtual bool canSendInstToNextStage(); + virtual bool canSendInstToStage(unsigned stage_num); /** Send an instruction to the next stage buffer */ virtual bool sendInstToNextStage(DynInstPtr inst); @@ -194,6 +194,9 @@ class PipelineStage */ virtual void skidInsert(unsigned tid); + /** Total size of all skid buffers */ + int skidSize(); + /** Returns if all of the skid buffers are empty. */ bool skidsEmpty(); -- cgit v1.2.3