From 078f914e69d6a08b0ff881b0909535307464553f Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Sun, 19 Jun 2011 21:43:42 -0400
Subject: inorder: SE mode TLB faults handle them like we do in FS mode, by
 blocking the TLB until the fault is handled by the fault->invoke()

---
 src/cpu/inorder/resources/cache_unit.cc | 37 ++++++++++++++++++---------------
 1 file changed, 20 insertions(+), 17 deletions(-)

(limited to 'src/cpu/inorder/resources/cache_unit.cc')

diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 350e2d1dd..8b487dd3f 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -178,10 +178,6 @@ CacheUnit::init()
         reqs[i] = new CacheRequest(this);
     }
 
-    // Currently Used to Model TLB Latency. Eventually
-    // Switch to Timing TLB translations.
-    resourceEvent = new CacheUnitEvent[width];
-
     cacheBlkSize = this->cachePort->peerBlockSize();
     cacheBlkMask = cacheBlkSize  - 1;
 
@@ -433,30 +429,22 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
     ThreadContext *tc = cpu->thread[tid]->getTC();
     PCState old_pc = tc->pcState();
     tc->pcState() = inst->pcState();
+
     inst->fault =
         _tlb->translateAtomic(cache_req->memReq, tc, tlb_mode);
     tc->pcState() = old_pc;
 
     if (inst->fault != NoFault) {
         DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
-                "addr:%08p for [sn:%i].\n", tid, inst->fault->name(),
+                "addr:%08p for [sn:%i].\n", tid, tlb_fault->name(),
                 cache_req->memReq->getVaddr(), inst->seqNum);
 
         tlbBlocked[tid] = true;
         tlbBlockSeqNum[tid] = inst->seqNum;
 
-#if !FULL_SYSTEM
-        unsigned stage_num = cache_req->getStageNum();
-
-        cpu->pipelineStage[stage_num]->setResStall(cache_req, tid);
-        cache_req->tlbStall = true;
-
-        // schedule a time to process the tlb miss.
-        // latency hardcoded to 1 (for now), but will be updated
-        // when timing translation gets added in
-        unsigned slot_idx = cache_req->getSlot();
-        scheduleEvent(slot_idx, 1);
-#endif
+        // Make sure nothing gets executed until after this faulting
+        // instruction gets handled.
+        inst->setSerializeAfter();
 
         // Mark it as complete so it can pass through next stage.
         // Fault Handling will happen at commit/graduation
@@ -467,8 +455,15 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
                 cache_req->memReq->getVaddr(),
                 cache_req->memReq->getPaddr());
     }
+}
 
+#if !FULL_SYSTEM
+void
+CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+{
+    tlbBlocked[tid] = false;
 }
+#endif
 
 Fault
 CacheUnit::read(DynInstPtr inst, Addr addr,
@@ -703,6 +698,14 @@ CacheUnit::execute(int slot_num)
         return;
     }
 
+    if (inst->isSquashed()) {
+        DPRINTF(InOrderCachePort,
+                "[tid:%i]: [sn:%i]: Detected squashed instruction "
+                "next stage.\n", inst->readTid(), inst->seqNum);
+        finishCacheUnitReq(inst, cache_req);
+        return;
+    }
+
 #if TRACING_ON
     ThreadID tid = inst->readTid();
     std::string acc_type = "write";
-- 
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