From ab3d37d398a59e15cec656ca2b8790a7bc19ad48 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Fri, 4 Feb 2011 00:08:20 -0500
Subject: inorder: implement separate fetch unit instead of having one
 cache-unit class be responsible for both data and code accesses, separate
 code that is just for fetch in it's own derived class off the original base
 class. This makes the code easier to manage as well as handle future cases of
 special fetch handling

---
 src/cpu/inorder/resources/cache_unit.hh | 41 ++++++++-------------------------
 1 file changed, 10 insertions(+), 31 deletions(-)

(limited to 'src/cpu/inorder/resources/cache_unit.hh')

diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index af8c4892c..69c1dbd9e 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -64,15 +64,10 @@ class CacheUnit : public Resource
               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
 
     enum Command {
-        InitiateFetch,
-        CompleteFetch,
         InitiateReadData,
         CompleteReadData,
         InitiateWriteData,
         CompleteWriteData,
-        Fetch,
-        ReadData,
-        WriteData,
         InitSecondSplitRead,
         InitSecondSplitWrite,
         CompleteSecondSplitRead,
@@ -125,39 +120,32 @@ class CacheUnit : public Resource
     void init();
 
     ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
-                                        int res_idx, int slot_num,
-                                        unsigned cmd);
+                                int res_idx, int slot_num,
+                                unsigned cmd);
 
     ResReqPtr findRequest(DynInstPtr inst);
     ResReqPtr findSplitRequest(DynInstPtr inst, int idx);
 
     void requestAgain(DynInstPtr inst, bool &try_request);
 
-    int getSlot(DynInstPtr inst);
+    virtual int getSlot(DynInstPtr inst);
 
-    /** Execute the function of this resource. The Default is action
-     *  is to do nothing. More specific models will derive from this
-     *  class and define their own execute function.
-     */
-    void execute(int slot_num);
+    /** Executes one of the commands from the "Command" enum */
+    virtual void execute(int slot_num);
 
-    void squash(DynInstPtr inst, int stage_num,
+    virtual void squash(DynInstPtr inst, int stage_num,
                 InstSeqNum squash_seq_num, ThreadID tid);
 
     void squashDueToMemStall(DynInstPtr inst, int stage_num,
                              InstSeqNum squash_seq_num, ThreadID tid);
 
-    /** Processes cache completion event. */
-    void processCacheCompletion(PacketPtr pkt);
+    /** After memory request is completedd in the cache, then do final
+        processing to complete the request in the CPU.
+    */
+   virtual void processCacheCompletion(PacketPtr pkt);
 
     void recvRetry();
 
-    /** Align a PC to the start of an I-cache block. */
-    Addr cacheBlockAlignPC(Addr addr)
-    {
-        return (addr & ~(cacheBlkMask));
-    }
-
     /** Returns a specific port. */
     Port *getPort(const std::string &if_name, int idx);
     
@@ -202,15 +190,6 @@ class CacheUnit : public Resource
         return (addr & ~(cacheBlkMask));
     }
 
-    /** The mem line being fetched. */
-    uint8_t *fetchData[ThePipeline::MaxThreads];
-
-    /** @TODO: Move functionaly of fetching more than
-        one instruction to 'fetch unit'*/
-    /** The Addr of the cacheline that has been loaded. */
-    //Addr cacheBlockAddr[ThePipeline::MaxThreads];
-    //unsigned fetchOffset[ThePipeline::MaxThreads];
-
     TheISA::Predecoder predecoder;
 
     bool tlbBlocked[ThePipeline::MaxThreads];
-- 
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