From 73cfab8b234c595e86413d4f7169bddc1a1184dd Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Sun, 19 Jun 2011 21:43:35 -0400
Subject: inorder: DynInst handling of stores for big-endian ISAs The DynInst
 was not performing the host-to-guest translation which ended up breaking
 stores for SPARC

---
 src/cpu/inorder/resources/cache_unit.cc | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/cpu/inorder/resources')

diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index c38e5541d..c1a3590be 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -840,6 +840,12 @@ CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res,
         } else {
             cache_req->dataPkt->dataStatic(&cache_req->inst->storeData);            
         }
+
+        DPRINTF(InOrderCachePort,
+                "[tid:%u]: [sn:%i]: Storing data: %s\n",
+                tid, inst->seqNum,
+                printMemData(cache_req->dataPkt->getPtr<uint8_t>(),
+                             cache_req->dataPkt->getSize()));
         
         if (cache_req->memReq->isCondSwap()) {
             assert(write_res);
-- 
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