From 00f24ae92c7b9aa73e12fd8160b5756e80126db2 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 3 Feb 2011 20:23:00 -0800 Subject: Config: Keep track of uncached and cached ports separately. This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches. --- src/cpu/inorder/InOrderCPU.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/inorder') diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index d6db346d4..8e25891e7 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -46,7 +46,7 @@ class InOrderCPU(BaseCPU): dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = ['icache_port', 'dcache_port'] + _cached_ports = ['icache_port', 'dcache_port'] predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") localPredictorSize = Param.Unsigned(2048, "Size of local predictor") -- cgit v1.2.3