From 2012202b06a620998709f605f8f8692ad718294d Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Tue, 12 May 2009 15:01:14 -0400
Subject: inorder/alpha-isa: create eaComp object visible to StaticInst through
 ISA Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead,
 create eaComp that is visible from StaticInst object. Gives InOrder model
 capability of generating address without actually initiating access * * *

---
 src/cpu/inorder/inorder_dyn_inst.cc | 16 ++++++++--------
 src/cpu/inorder/pipeline_traits.cc  |  3 ++-
 2 files changed, 10 insertions(+), 9 deletions(-)

(limited to 'src/cpu/inorder')

diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index 7fc953da2..b6eac04cb 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -225,6 +225,13 @@ InOrderDynInst::execute()
     return this->fault;
 }
 
+Fault
+InOrderDynInst::calcEA()
+{
+    this->fault = this->staticInst->eaComp(this, this->traceData);
+    return this->fault;
+}
+
 Fault
 InOrderDynInst::initiateAcc()
 {
@@ -274,17 +281,10 @@ void InOrderDynInst::deleteStages() {
     }
 }
 
-Fault
-InOrderDynInst::calcEA()
-{
-    return staticInst->eaCompInst()->execute(this, this->traceData);
-}
-
 Fault
 InOrderDynInst::memAccess()
 {
-    //return staticInst->memAccInst()->execute(this, this->traceData);
-    return initiateAcc( );
+    return initiateAcc();
 }
 
 void
diff --git a/src/cpu/inorder/pipeline_traits.cc b/src/cpu/inorder/pipeline_traits.cc
index eb899452a..1c17b0d3f 100644
--- a/src/cpu/inorder/pipeline_traits.cc
+++ b/src/cpu/inorder/pipeline_traits.cc
@@ -99,8 +99,8 @@ bool createBackEndSchedule(DynInstPtr &inst)
     if ( inst->isNonSpeculative() ) {
         // skip execution of non speculative insts until later
     } else if ( inst->isMemRef() ) {
-        E->needs(AGEN, AGENUnit::GenerateAddr);
         if ( inst->isLoad() ) {
+            E->needs(AGEN, AGENUnit::GenerateAddr);
             E->needs(DTLB, TLBUnit::DataLookup);
             E->needs(DCache, CacheUnit::InitiateReadData);
         }
@@ -121,6 +121,7 @@ bool createBackEndSchedule(DynInstPtr &inst)
         M->needs(DCache, CacheUnit::CompleteReadData);
     } else if ( inst->isStore() ) {
         M->needs(RegManager, UseDefUnit::ReadSrcReg, 1);
+        M->needs(AGEN, AGENUnit::GenerateAddr);
         M->needs(DTLB, TLBUnit::DataLookup);
         M->needs(DCache, CacheUnit::InitiateWriteData);
     }
-- 
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