From 25884a87733cd35ef6613aaef9a8a08194267552 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:20 -0700 Subject: Registers: Get rid of the float register width parameter. --- src/cpu/inorder/cpu.cc | 18 ++++++------ src/cpu/inorder/cpu.hh | 12 +++----- src/cpu/inorder/inorder_dyn_inst.cc | 43 ++++++++--------------------- src/cpu/inorder/inorder_dyn_inst.hh | 28 ++++++------------- src/cpu/inorder/resources/execution_unit.cc | 3 +- src/cpu/inorder/resources/use_def.cc | 23 ++++++--------- src/cpu/inorder/thread_context.cc | 25 ----------------- src/cpu/inorder/thread_context.hh | 8 ------ 8 files changed, 40 insertions(+), 120 deletions(-) (limited to 'src/cpu/inorder') diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 51d62e179..fc8723829 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -890,16 +890,15 @@ InOrderCPU::readIntReg(int reg_idx, ThreadID tid) } FloatReg -InOrderCPU::readFloatReg(int reg_idx, ThreadID tid, int width) +InOrderCPU::readFloatReg(int reg_idx, ThreadID tid) { - - return floatRegFile[tid].readReg(reg_idx, width); + return floatRegFile[tid].readReg(reg_idx); } FloatRegBits -InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid, int width) +InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid) {; - return floatRegFile[tid].readRegBits(reg_idx, width); + return floatRegFile[tid].readRegBits(reg_idx); } void @@ -910,17 +909,16 @@ InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid) void -InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid, int width) +InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid) { - floatRegFile[tid].setReg(reg_idx, val, width); + floatRegFile[tid].setReg(reg_idx, val); } void -InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid, - int width) +InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid) { - floatRegFile[tid].setRegBits(reg_idx, val, width); + floatRegFile[tid].setRegBits(reg_idx, val); } uint64_t diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index bfc5139cf..bda4c41bd 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -404,19 +404,15 @@ class InOrderCPU : public BaseCPU /** Register file accessors */ uint64_t readIntReg(int reg_idx, ThreadID tid); - FloatReg readFloatReg(int reg_idx, ThreadID tid, - int width = TheISA::SingleWidth); + FloatReg readFloatReg(int reg_idx, ThreadID tid); - FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid, - int width = TheISA::SingleWidth); + FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid); void setIntReg(int reg_idx, uint64_t val, ThreadID tid); - void setFloatReg(int reg_idx, FloatReg val, ThreadID tid, - int width = TheISA::SingleWidth); + void setFloatReg(int reg_idx, FloatReg val, ThreadID tid); - void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid, - int width = TheISA::SingleWidth); + void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid); /** Reads a miscellaneous register. */ MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index ee2e5500e..a6abb28b2 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -366,14 +366,9 @@ InOrderDynInst::setIntSrc(int idx, uint64_t val) /** Records an fp register being set to a value. */ void -InOrderDynInst::setFloatSrc(int idx, FloatReg val, int width) +InOrderDynInst::setFloatSrc(int idx, FloatReg val) { - if (width == 32) - instSrc[idx].dbl = val; - else if (width == 64) - instSrc[idx].dbl = val; - else - panic("Unsupported width!"); + instSrc[idx].dbl = val; } /** Records an fp register being set to an integer value. */ @@ -394,22 +389,15 @@ InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid) /** Reads a FP register. */ FloatReg -InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx, int width) -{ - if (width == 32) - return (float)instSrc[idx].dbl; - else if (width == 64) - return instSrc[idx].dbl; - else { - panic("Unsupported Floating Point Width!"); - return 0; - } +InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx) +{ + return instSrc[idx].dbl; } /** Reads a FP register as a integer. */ FloatRegBits -InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx, int width) +InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx) { return instSrc[idx].integer; } @@ -507,31 +495,22 @@ InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val) /** Sets a FP register. */ void -InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, int width) -{ - if (width == 32) { - instResult[idx].val.dbl = (float)val; - instResult[idx].type = Float; - } else if (width == 64) { - instResult[idx].val.dbl = val; - instResult[idx].type = Double; - } else { - panic("Unsupported Floating Point Width!"); - } +InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) +{ + instResult[idx].val.dbl = val; + instResult[idx].type = Float; instResult[idx].tick = curTick; - instResult[idx].width = width; } /** Sets a FP register as a integer. */ void InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) + FloatRegBits val) { instResult[idx].type = Integer; instResult[idx].val.integer = val; instResult[idx].tick = curTick; - instResult[idx].width = width; } /** Sets a misc. register. */ diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh index 031d882ee..e95a6d039 100644 --- a/src/cpu/inorder/inorder_dyn_inst.hh +++ b/src/cpu/inorder/inorder_dyn_inst.hh @@ -243,10 +243,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted ResultType type; InstValue val; Tick tick; - int width; InstResult() - : type(None), tick(0), width(0) + : type(None), tick(0) {} }; @@ -817,7 +816,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** Functions that sets an integer or floating point * source register to a value. */ void setIntSrc(int idx, uint64_t val); - void setFloatSrc(int idx, FloatReg val, int width = 32); + void setFloatSrc(int idx, FloatReg val); void setFloatRegBitsSrc(int idx, uint64_t val); uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; } @@ -830,10 +829,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted * the source reg. value is set using the setSrcReg() function. */ IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0); - FloatReg readFloatRegOperand(const StaticInst *si, int idx, - int width = TheISA::SingleWidth); - TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width = TheISA::SingleWidth); + FloatReg readFloatRegOperand(const StaticInst *si, int idx); + TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); MiscReg readMiscReg(int misc_reg); MiscReg readMiscRegNoEffect(int misc_reg); MiscReg readMiscRegOperand(const StaticInst *si, int idx); @@ -853,15 +850,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** Depending on type, return Float or Double */ double readFloatResult(int idx) { - //Should this function have a parameter for what width of return?x - return (instResult[idx].type == Float) ? - (float) instResult[idx].val.dbl : instResult[idx].val.dbl; - } - - double readDoubleResult(int idx) - { - assert(instResult[idx].type == Double); - return instResult[idx].val.dbl; + return instResult[idx].val.dbl; } Tick readResultTime(int idx) { return instResult[idx].tick; } @@ -872,10 +861,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted * it's destination register. */ void setIntRegOperand(const StaticInst *si, int idx, IntReg val); - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width = TheISA::SingleWidth); - void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val, - int width = TheISA::SingleWidth); + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); + void setFloatRegOperandBits(const StaticInst *si, int idx, + TheISA::FloatRegBits val); void setMiscReg(int misc_reg, const MiscReg &val); void setMiscRegNoEffect(int misc_reg, const MiscReg &val); void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val); diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc index c9072b5d5..6c44e2456 100644 --- a/src/cpu/inorder/resources/execution_unit.cc +++ b/src/cpu/inorder/resources/execution_unit.cc @@ -179,8 +179,7 @@ ExecutionUnit::execute(int slot_num) DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n", inst->readTid(), seq_num, (inst->resultType(0) == InOrderDynInst::Float) ? - inst->readFloatResult(0) : (inst->resultType(0) == InOrderDynInst::Double) ? - inst->readDoubleResult(0) : inst->readIntResult(0)); + inst->readFloatResult(0) : inst->readIntResult(0)); exec_req->done(); } else { diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc index b30a3a1bf..2f1652c08 100644 --- a/src/cpu/inorder/resources/use_def.cc +++ b/src/cpu/inorder/resources/use_def.cc @@ -53,8 +53,6 @@ UseDefUnit::UseDefUnit(string res_name, int res_id, int res_width, outWriteSeqNum[tid] = maxSeqNum; regDepMap[tid] = &cpu->archRegDepMap[tid]; - - floatRegSize[tid] = cpu->floatRegFile[tid].regWidth; } } @@ -138,12 +136,11 @@ UseDefUnit::execute(int slot_idx) DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i from Register File:%x (%08f).\n", tid, reg_idx, - cpu->readFloatRegBits(reg_idx, inst->readTid(), floatRegSize[tid]), - cpu->readFloatReg(reg_idx, inst->readTid(),floatRegSize[tid])); + cpu->readFloatRegBits(reg_idx, inst->readTid()), + cpu->readFloatReg(reg_idx, inst->readTid())); inst->setFloatSrc(ud_idx, - cpu->readFloatReg(reg_idx, inst->readTid(), floatRegSize[tid]), - floatRegSize[tid]); + cpu->readFloatReg(reg_idx, inst->readTid())); } else { reg_idx -= Ctrl_Base_DepTag; DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i from Register File:%i.\n", @@ -183,8 +180,7 @@ UseDefUnit::execute(int slot_idx) tid, forward_inst->readFloatResult(dest_reg_idx) , forward_inst->seqNum, inst->seqNum, ud_idx); inst->setFloatSrc(ud_idx, - forward_inst->readFloatResult(dest_reg_idx), - floatRegSize[tid]); + forward_inst->readFloatResult(dest_reg_idx)); } else { DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest. reg value 0x%x from " "[sn:%i] to [sn:%i] source #%i.\n", @@ -244,24 +240,21 @@ UseDefUnit::execute(int slot_idx) cpu->setFloatRegBits(reg_idx, // Check for FloatRegBits Here inst->readIntResult(ud_idx), - inst->readTid(), - floatRegSize[tid]); + inst->readTid()); } else if (inst->resultType(ud_idx) == InOrderDynInst::Float) { DPRINTF(InOrderUseDef, "[tid:%i]: Writing Float Result 0x%x (bits:0x%x) to register idx %i.\n", tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx); cpu->setFloatReg(reg_idx, inst->readFloatResult(ud_idx), - inst->readTid(), - floatRegSize[tid]); + inst->readTid()); } else if (inst->resultType(ud_idx) == InOrderDynInst::Double) { DPRINTF(InOrderUseDef, "[tid:%i]: Writing Double Result 0x%x (bits:0x%x) to register idx %i.\n", tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx); cpu->setFloatReg(reg_idx, // Check for FloatRegBits Here - inst->readDoubleResult(ud_idx), - inst->readTid(), - floatRegSize[tid]); + inst->readFloatResult(ud_idx), + inst->readTid()); } else { panic("Result Type Not Set For [sn:%i] %s.\n", inst->seqNum, inst->instName()); } diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc index a1e9b5948..fe1a0faa1 100644 --- a/src/cpu/inorder/thread_context.cc +++ b/src/cpu/inorder/thread_context.cc @@ -150,24 +150,12 @@ InOrderThreadContext::readIntReg(int reg_idx) return cpu->readIntReg(reg_idx, thread->readTid()); } -FloatReg -InOrderThreadContext::readFloatReg(int reg_idx, int width) -{ - return cpu->readFloatReg(reg_idx, thread->readTid(), width); -} - FloatReg InOrderThreadContext::readFloatReg(int reg_idx) { return cpu->readFloatReg(reg_idx, thread->readTid()); } -FloatRegBits -InOrderThreadContext::readFloatRegBits(int reg_idx, int width) -{ - return cpu->readFloatRegBits(reg_idx, thread->readTid(), width); -} - FloatRegBits InOrderThreadContext::readFloatRegBits(int reg_idx) { @@ -186,25 +174,12 @@ InOrderThreadContext::setIntReg(int reg_idx, uint64_t val) cpu->setIntReg(reg_idx, val, thread->readTid()); } -void -InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val, int width) -{ - cpu->setFloatReg(reg_idx, val, thread->readTid(), width); -} - void InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val) { cpu->setFloatReg(reg_idx, val, thread->readTid()); } -void -InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val, - int width) -{ - cpu->setFloatRegBits(reg_idx, val, thread->readTid(), width); -} - void InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val) { diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index aac8901b3..327f8ac71 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -152,12 +152,8 @@ class InOrderThreadContext : public ThreadContext /** Reads an integer register. */ virtual uint64_t readIntReg(int reg_idx); - virtual FloatReg readFloatReg(int reg_idx, int width); - virtual FloatReg readFloatReg(int reg_idx); - virtual FloatRegBits readFloatRegBits(int reg_idx, int width); - virtual FloatRegBits readFloatRegBits(int reg_idx); virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid); @@ -165,12 +161,8 @@ class InOrderThreadContext : public ThreadContext /** Sets an integer register to a value. */ virtual void setIntReg(int reg_idx, uint64_t val); - virtual void setFloatReg(int reg_idx, FloatReg val, int width); - virtual void setFloatReg(int reg_idx, FloatReg val); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val); virtual void setRegOtherThread(int misc_reg, const MiscReg &val, -- cgit v1.2.3