From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001 From: Yasuko Eckert Date: Tue, 15 Oct 2013 14:22:44 -0400 Subject: cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. --- src/cpu/inorder/cpu.cc | 32 ++++++++++++++++++++++++++++++++ src/cpu/inorder/cpu.hh | 8 ++++++++ src/cpu/inorder/inorder_dyn_inst.cc | 4 ++++ src/cpu/inorder/inorder_dyn_inst.hh | 9 +++++++++ src/cpu/inorder/thread_context.cc | 31 +++++++++++++++++++++++++++++++ src/cpu/inorder/thread_context.hh | 11 +++++++++++ 6 files changed, 95 insertions(+) (limited to 'src/cpu/inorder') diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 32ca2caaf..5a02f94d9 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -361,6 +361,9 @@ InOrderCPU::InOrderCPU(Params *params) memset(intRegs[tid], 0, sizeof(intRegs[tid])); memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid])); +#ifdef ISA_HAS_CC_REGS + memset(ccRegs[tid], 0, sizeof(ccRegs[tid])); +#endif isa[tid]->clear(); // Define dummy instructions and resource requests to be used. @@ -1305,6 +1308,19 @@ InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid) return floatRegs.i[tid][reg_idx]; } +CCReg +InOrderCPU::readCCReg(RegIndex reg_idx, ThreadID tid) +{ +#ifdef ISA_HAS_CC_REGS + DPRINTF(CCRegs, "[tid:%i]: Reading CC. Reg %i as %x\n", + tid, reg_idx, ccRegs[tid][reg_idx]); + + return ccRegs[tid][reg_idx]; +#else + panic("readCCReg: ISA does not have CC regs\n"); +#endif +} + void InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid) { @@ -1344,6 +1360,18 @@ InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid) floatRegs.f[tid][reg_idx]); } +void +InOrderCPU::setCCReg(RegIndex reg_idx, CCReg val, ThreadID tid) +{ +#ifdef ISA_HAS_CC_REGS + DPRINTF(CCRegs, "[tid:%i]: Setting CC. Reg %i to %x\n", + tid, reg_idx, val); + ccRegs[tid][reg_idx] = val; +#else + panic("readCCReg: ISA does not have CC regs\n"); +#endif +} + uint64_t InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid) { @@ -1391,6 +1419,10 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val, setFloatRegBits(rel_idx, val, tid); break; + case CCRegClass: + setCCReg(rel_idx, val, tid); + break; + case MiscRegClass: setMiscReg(rel_idx, val, tid); // Misc. Register File break; diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index d5a31cca8..1183f6fc9 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -93,6 +93,7 @@ class InOrderCPU : public BaseCPU typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; + typedef TheISA::CCReg CCReg; typedef TheISA::MiscReg MiscReg; typedef TheISA::RegIndex RegIndex; @@ -327,6 +328,9 @@ class InOrderCPU : public BaseCPU FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; } floatRegs; TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs]; +#ifdef ISA_HAS_CC_REGS + TheISA::CCReg ccRegs[ThePipeline::MaxThreads][TheISA::NumCCRegs]; +#endif /** ISA state */ std::vector isa; @@ -590,12 +594,16 @@ class InOrderCPU : public BaseCPU FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid); + CCReg readCCReg(RegIndex reg_idx, ThreadID tid); + void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid); void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid); void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid); + void setCCReg(RegIndex reg_idx, CCReg val, ThreadID tid); + RegIndex flattenRegIdx(RegIndex reg_idx, RegClass ®_type, ThreadID tid); /** Reads a miscellaneous register. */ diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index c2765a3ba..aedc630f5 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -562,6 +562,10 @@ InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val, this->cpu->setFloatRegBits(rel_idx, val, tid); break; + case CCRegClass: + this->cpu->setCCReg(rel_idx, val, tid); + break; + case MiscRegClass: this->cpu->setMiscReg(rel_idx, val, tid); // Misc. Register File break; diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh index afd137a2e..48c15e292 100644 --- a/src/cpu/inorder/inorder_dyn_inst.hh +++ b/src/cpu/inorder/inorder_dyn_inst.hh @@ -1,6 +1,7 @@ /* * Copyright (c) 2007 MIPS Technologies, Inc. * Copyright (c) 2004-2006 The Regents of The University of Michigan + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -87,6 +88,8 @@ class InOrderDynInst : public RefCounted typedef TheISA::FloatReg FloatReg; // Floating point register type. typedef TheISA::FloatRegBits FloatRegBits; + // Condition code register type. + typedef TheISA::CCReg CCReg; // Floating point register type. typedef TheISA::MiscReg MiscReg; @@ -880,6 +883,11 @@ class InOrderDynInst : public RefCounted return instResult[idx].res.fpVal.i; } + CCReg readCCResult(int idx) + { + return instResult[idx].res.intVal; + } + Tick readResultTime(int idx) { return instResult[idx].tick; } IntReg* getIntResultPtr(int idx) { return &instResult[idx].res.intVal; } @@ -891,6 +899,7 @@ class InOrderDynInst : public RefCounted void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val); + void setCCRegOperand(const StaticInst *si, int idx, CCReg val); void setMiscReg(int misc_reg, const MiscReg &val); void setMiscRegNoEffect(int misc_reg, const MiscReg &val); void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val); diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc index aab8c226a..763cc6df2 100644 --- a/src/cpu/inorder/thread_context.cc +++ b/src/cpu/inorder/thread_context.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * * The license below extends only to copyright in the software and shall @@ -190,6 +191,14 @@ InOrderThreadContext::readFloatRegBits(int reg_idx) return cpu->readFloatRegBits(reg_idx, tid); } +CCReg +InOrderThreadContext::readCCReg(int reg_idx) +{ + ThreadID tid = thread->threadId(); + reg_idx = cpu->isa[tid]->flattenCCIndex(reg_idx); + return cpu->readCCReg(reg_idx, tid); +} + uint64_t InOrderThreadContext::readRegOtherThread(int reg_idx, ThreadID tid) { @@ -220,6 +229,14 @@ InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val) cpu->setFloatRegBits(reg_idx, val, tid); } +void +InOrderThreadContext::setCCReg(int reg_idx, CCReg val) +{ + ThreadID tid = thread->threadId(); + reg_idx = cpu->isa[tid]->flattenCCIndex(reg_idx); + cpu->setCCReg(reg_idx, val, tid); +} + void InOrderThreadContext::setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) @@ -281,3 +298,17 @@ InOrderThreadContext::setFloatRegBitsFlat(int idx, FloatRegBits val) const ThreadID tid = thread->threadId(); cpu->setFloatRegBits(idx, val, tid); } + +CCReg +InOrderThreadContext::readCCRegFlat(int idx) +{ + const ThreadID tid = thread->threadId(); + return cpu->readCCReg(idx, tid); +} + +void +InOrderThreadContext::setCCRegFlat(int idx, CCReg val) +{ + const ThreadID tid = thread->threadId(); + cpu->setCCReg(idx, val, tid); +} diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index f4847d0b4..5e1c65f8f 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * * The license below extends only to copyright in the software and shall @@ -207,6 +208,8 @@ class InOrderThreadContext : public ThreadContext FloatRegBits readFloatRegBits(int reg_idx); + CCReg readCCReg(int reg_idx); + uint64_t readRegOtherThread(int misc_reg, ThreadID tid); /** Sets an integer register to a value. */ @@ -216,6 +219,8 @@ class InOrderThreadContext : public ThreadContext void setFloatRegBits(int reg_idx, FloatRegBits val); + void setCCReg(int reg_idx, CCReg val); + void setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid); @@ -265,6 +270,9 @@ class InOrderThreadContext : public ThreadContext int flattenFloatIndex(int reg) { return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); } + int flattenCCIndex(int reg) + { return cpu->isa[thread->threadId()]->flattenCCIndex(reg); } + void activateContext(Cycles delay) { cpu->activateContext(thread->threadId(), delay); } @@ -307,6 +315,9 @@ class InOrderThreadContext : public ThreadContext FloatRegBits readFloatRegBitsFlat(int idx); void setFloatRegBitsFlat(int idx, FloatRegBits val); + + CCReg readCCRegFlat(int idx); + void setCCRegFlat(int idx, CCReg val); }; #endif -- cgit v1.2.3