From 98cf57fb89b76a8ca423083d52cc647c7923fe51 Mon Sep 17 00:00:00 2001
From: Geoffrey Blake <geoffrey.blake@arm.com>
Date: Fri, 9 Mar 2012 09:59:28 -0500
Subject: CheckerCPU: Add function stubs to non-ARM ISA source to compile with
 CheckerCPU

Making the CheckerCPU a runtime time option requires the code to be compatible
with ISAs other than ARM.  This patch adds the appropriate function
stubs to allow compilation.
---
 src/cpu/inorder/thread_context.hh | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'src/cpu/inorder')

diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 0f9b1028e..aaf7d6ede 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -40,6 +40,7 @@
 #include "arch/kernel_stats.hh"
 
 class EndQuiesceEvent;
+class CheckerCPU;
 namespace Kernel {
     class Statistics;
 };
@@ -76,6 +77,12 @@ class InOrderThreadContext : public ThreadContext
     /** @TODO: PERF: Should we bind this to a pointer in constructor? */
     TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
 
+    /** Currently InOrder model does not support CheckerCPU, this is
+     *  merely here for supporting compilation of gem5 with the Checker
+     *  as a runtime option
+     */
+    CheckerCPU *getCheckerCpuPtr() { return NULL; }
+
     Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
 
     System *getSystemPtr() { return cpu->system; }
@@ -215,6 +222,12 @@ class InOrderThreadContext : public ThreadContext
     void pcState(const TheISA::PCState &val)
     { cpu->pcState(val, thread->threadId()); }
 
+    /** Needs to be implemented for future CheckerCPU support.
+     *  See O3CPU for examples on how to integrate Checker.
+     */
+    void pcStateNoRecord(const TheISA::PCState &val)
+    {}
+
     Addr instAddr()
     { return cpu->instAddr(thread->threadId()); }
 
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