From cc1feb9f6ddf9d0a58365ffa9f7ae948bf19901d Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Thu, 19 Oct 2006 21:07:53 -0400
Subject: Fix memtester to use functional access, fix cache to work
functionally now that we could test it.
src/cpu/memtest/memtest.cc:
Fix memtest to do functional accesses
src/mem/cache/cache_impl.hh:
Fix cache to handle functional accesses properly based on memtester changes
Still need to fix functional accesses in timing mode now that the memtester can test it.
--HG--
extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
---
src/cpu/memtest/memtest.cc | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
(limited to 'src/cpu/memtest/memtest.cc')
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 024cd7e41..cb643e5d9 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -72,8 +72,8 @@ void
MemTest::CpuPort::recvFunctional(Packet *pkt)
{
//Do nothing if we see one come through
- if (curTick != 0)//Supress warning durring initialization
- warn("Functional Writes not implemented in MemTester\n");
+// if (curTick != 0)//Supress warning durring initialization
+// warn("Functional Writes not implemented in MemTester\n");
//Need to find any response values that intersect and update
return;
}
@@ -345,8 +345,8 @@ MemTest::tick()
} else {
paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
}
- //bool probe = (random() % 2 == 1) && !req->isUncacheable();
- bool probe = false;
+ bool probe = (random() % 2 == 1) && !(flags & UNCACHEABLE);
+ //bool probe = false;
paddr &= ~((1 << access_size) - 1);
req->setPhys(paddr, 1 << access_size, flags);
@@ -388,6 +388,7 @@ MemTest::tick()
if (probe) {
cachePort.sendFunctional(pkt);
+ pkt->makeAtomicResponse();
completeRequest(pkt);
} else {
// req->completionEvent = new MemCompleteEvent(req, result, this);
@@ -431,6 +432,7 @@ MemTest::tick()
if (probe) {
cachePort.sendFunctional(pkt);
+ pkt->makeAtomicResponse();
completeRequest(pkt);
} else {
// req->completionEvent = new MemCompleteEvent(req, NULL, this);
--
cgit v1.2.3
From 7245d4530d0c8367fa7b1adadcb55e1e8bd466e7 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <binkertn@umich.edu>
Date: Thu, 19 Oct 2006 23:38:45 -0700
Subject: refactor code for the packet, get rid of packet_impl.hh and call it
packet_access.hh and fix the #includes so things compile right.
--HG--
extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
---
src/cpu/memtest/memtest.cc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
(limited to 'src/cpu/memtest/memtest.cc')
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index cb643e5d9..23f2eacbc 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -38,17 +38,17 @@
#include "base/misc.hh"
#include "base/statistics.hh"
-//#include "cpu/simple_thread.hh"
#include "cpu/memtest/memtest.hh"
+//#include "cpu/simple_thread.hh"
//#include "mem/cache/base_cache.hh"
+#include "mem/mem_object.hh"
+#include "mem/port.hh"
+#include "mem/packet.hh"
//#include "mem/physical.hh"
+#include "mem/request.hh"
#include "sim/builder.hh"
#include "sim/sim_events.hh"
#include "sim/stats.hh"
-#include "mem/packet.hh"
-#include "mem/request.hh"
-#include "mem/port.hh"
-#include "mem/mem_object.hh"
using namespace std;
--
cgit v1.2.3
From a4c6f0d69eda5d23b12576080d532ddf768fbdbe Mon Sep 17 00:00:00 2001
From: Nathan Binkert <binkertn@umich.edu>
Date: Fri, 20 Oct 2006 00:10:12 -0700
Subject: Use PacketPtr everywhere
--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
---
src/cpu/memtest/memtest.cc | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
(limited to 'src/cpu/memtest/memtest.cc')
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 23f2eacbc..1e0d07f9a 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -55,21 +55,21 @@ using namespace std;
int TESTER_ALLOCATOR=0;
bool
-MemTest::CpuPort::recvTiming(Packet *pkt)
+MemTest::CpuPort::recvTiming(PacketPtr pkt)
{
memtest->completeRequest(pkt);
return true;
}
Tick
-MemTest::CpuPort::recvAtomic(Packet *pkt)
+MemTest::CpuPort::recvAtomic(PacketPtr pkt)
{
panic("MemTest doesn't expect recvAtomic callback!");
return curTick;
}
void
-MemTest::CpuPort::recvFunctional(Packet *pkt)
+MemTest::CpuPort::recvFunctional(PacketPtr pkt)
{
//Do nothing if we see one come through
// if (curTick != 0)//Supress warning durring initialization
@@ -94,7 +94,7 @@ MemTest::CpuPort::recvRetry()
}
void
-MemTest::sendPkt(Packet *pkt) {
+MemTest::sendPkt(PacketPtr pkt) {
if (atomic) {
cachePort.sendAtomic(pkt);
pkt->makeAtomicResponse();
@@ -204,7 +204,7 @@ printData(ostream &os, uint8_t *data, int nbytes)
}
void
-MemTest::completeRequest(Packet *pkt)
+MemTest::completeRequest(PacketPtr pkt)
{
MemTestSenderState *state =
dynamic_cast<MemTestSenderState *>(pkt->senderState);
@@ -381,7 +381,7 @@ MemTest::tick()
<< dec << curTick << endl;
}
- Packet *pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
MemTestSenderState *state = new MemTestSenderState(result);
pkt->senderState = state;
@@ -421,7 +421,7 @@ MemTest::tick()
<< dec << curTick << endl;
}
*/
- Packet *pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
uint8_t *pkt_data = new uint8_t[req->getSize()];
pkt->dataDynamicArray(pkt_data);
memcpy(pkt_data, &data, req->getSize());
--
cgit v1.2.3
From 28e9641c2cf063d8ee1eba9f440dfcda9c82d965 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Fri, 20 Oct 2006 13:01:21 -0400
Subject: Use fixPacket function everywhere. Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its
queue on a read.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
---
src/cpu/memtest/memtest.cc | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
(limited to 'src/cpu/memtest/memtest.cc')
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index cb643e5d9..a99fe7e07 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -113,7 +113,7 @@ MemTest::MemTest(const string &name,
// PhysicalMemory *check_mem,
unsigned _memorySize,
unsigned _percentReads,
-// unsigned _percentCopies,
+ unsigned _percentFunctional,
unsigned _percentUncacheable,
unsigned _progressInterval,
unsigned _percentSourceUnaligned,
@@ -130,7 +130,7 @@ MemTest::MemTest(const string &name,
// checkMem(check_mem),
size(_memorySize),
percentReads(_percentReads),
-// percentCopies(_percentCopies),
+ percentFunctional(_percentFunctional),
percentUncacheable(_percentUncacheable),
progressInterval(_progressInterval),
nextProgressMessage(_progressInterval),
@@ -345,7 +345,7 @@ MemTest::tick()
} else {
paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
}
- bool probe = (random() % 2 == 1) && !(flags & UNCACHEABLE);
+ bool probe = (random() % 100 < percentFunctional) && !(flags & UNCACHEABLE);
//bool probe = false;
paddr &= ~((1 << access_size) - 1);
@@ -501,7 +501,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
// SimObjectParam<PhysicalMemory *> check_mem;
Param<unsigned> memory_size;
Param<unsigned> percent_reads;
-// Param<unsigned> percent_copies;
+ Param<unsigned> percent_functional;
Param<unsigned> percent_uncacheable;
Param<unsigned> progress_interval;
Param<unsigned> percent_source_unaligned;
@@ -520,7 +520,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
// INIT_PARAM(check_mem, "check memory"),
INIT_PARAM(memory_size, "memory size"),
INIT_PARAM(percent_reads, "target read percentage"),
-// INIT_PARAM(percent_copies, "target copy percentage"),
+ INIT_PARAM(percent_functional, "percentage of access that are functional"),
INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
INIT_PARAM(percent_source_unaligned,
@@ -537,7 +537,7 @@ END_INIT_SIM_OBJECT_PARAMS(MemTest)
CREATE_SIM_OBJECT(MemTest)
{
return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
- /*check_mem,*/ memory_size, percent_reads, /*percent_copies,*/
+ /*check_mem,*/ memory_size, percent_reads, percent_functional,
percent_uncacheable, progress_interval,
percent_source_unaligned, percent_dest_unaligned,
trace_addr, max_loads, atomic);
--
cgit v1.2.3