From 41dde5f6fdf195b8d51d70119737c5e3f7391f78 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 22 May 2007 06:32:24 -0700 Subject: memtest.hh: Fix description string. Minor whitespace cleanup. src/cpu/memtest/memtest.hh: Fix description string. Minor whitespace cleanup. --HG-- extra : convert_revision : 0c7213d088da46de9713ca6beabc30523ccb1c8c --- src/cpu/memtest/memtest.hh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/memtest') diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh index 264309fd7..84e16b98a 100644 --- a/src/cpu/memtest/memtest.hh +++ b/src/cpu/memtest/memtest.hh @@ -85,13 +85,13 @@ class MemTest : public MemObject TickEvent(MemTest *c) : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {} void process() {cpu->tick();} - virtual const char *description() { return "tick event"; } + virtual const char *description() { return "MemTest tick"; } }; TickEvent tickEvent; + class CpuPort : public Port { - MemTest *memtest; public: -- cgit v1.2.3 From 35cf19d441ed15d054d00674ec67ab5bc769f6d7 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sun, 17 Jun 2007 17:27:53 -0700 Subject: More major reorg of cache. Seems to work for atomic mode now, timing mode still broken. configs/example/memtest.py: Revamp options. src/cpu/memtest/memtest.cc: No need for memory initialization. No need to make atomic response... memory system should do that now. src/cpu/memtest/memtest.hh: MemTest really doesn't want to snoop. src/mem/bridge.cc: checkFunctional() cleanup. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.cc: src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/coherence_protocol.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/miss/SConscript: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: src/mem/packet.cc: src/mem/packet.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/tport.cc: More major reorg. Seems to work for atomic mode now, timing mode still broken. --HG-- extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87 --- src/cpu/memtest/memtest.cc | 28 +++++++--------------------- src/cpu/memtest/memtest.hh | 2 +- 2 files changed, 8 insertions(+), 22 deletions(-) (limited to 'src/cpu/memtest') diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc index 607cf1066..5d89f1b82 100644 --- a/src/cpu/memtest/memtest.cc +++ b/src/cpu/memtest/memtest.cc @@ -102,7 +102,6 @@ void MemTest::sendPkt(PacketPtr pkt) { if (atomic) { cachePort.sendAtomic(pkt); - pkt->makeAtomicResponse(); completeRequest(pkt); } else if (!cachePort.sendTiming(pkt)) { @@ -165,8 +164,6 @@ MemTest::MemTest(const string &name, tickEvent.schedule(0); id = TESTER_ALLOCATOR++; - if (TESTER_ALLOCATOR > 8) - panic("False sharing memtester only allows up to 8 testers"); accessRetry = false; } @@ -190,14 +187,8 @@ MemTest::init() blockAddrMask = blockSize - 1; traceBlockAddr = blockAddr(traceBlockAddr); - // set up intial memory contents here - - cachePort.memsetBlob(baseAddr1, 1, size); - funcPort.memsetBlob(baseAddr1, 1, size); - cachePort.memsetBlob(baseAddr2, 2, size); - funcPort.memsetBlob(baseAddr2, 2, size); - cachePort.memsetBlob(uncacheAddr, 3, size); - funcPort.memsetBlob(uncacheAddr, 3, size); + // initial memory contents for both physical memory and functional + // memory should be 0; no need to initialize them. } static void @@ -230,15 +221,10 @@ MemTest::completeRequest(PacketPtr pkt) case MemCmd::ReadResp: if (memcmp(pkt_data, data, pkt->getSize()) != 0) { - cerr << name() << ": on read of 0x" << hex << req->getPaddr() - << " (0x" << hex << blockAddr(req->getPaddr()) << ")" - << "@ cycle " << dec << curTick - << ", cache returns 0x"; - printData(cerr, pkt_data, pkt->getSize()); - cerr << ", expected 0x"; - printData(cerr, data, pkt->getSize()); - cerr << endl; - fatal(""); + panic("%s: read of %x (blk %x) @ cycle %d " + "returns %x, expected %x\n", name(), + req->getPaddr(), blockAddr(req->getPaddr()), curTick, + *pkt_data, *data); } numReads++; @@ -267,7 +253,7 @@ MemTest::completeRequest(PacketPtr pkt) break; */ default: - panic("invalid command"); + panic("invalid command %s (%d)", pkt->cmdString(), pkt->cmd.toInt()); } if (blockAddr(req->getPaddr()) == traceBlockAddr) { diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh index a6b08d61c..565fafb77 100644 --- a/src/cpu/memtest/memtest.hh +++ b/src/cpu/memtest/memtest.hh @@ -116,7 +116,7 @@ class MemTest : public MemObject virtual void getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) - { resp.clear(); snoop = true; } + { resp.clear(); snoop = false; } }; CpuPort cachePort; -- cgit v1.2.3