From c0d613adb4eca09c32aca1cc90f04c29574f69c6 Mon Sep 17 00:00:00 2001 From: Anouk Van Laer Date: Fri, 17 Mar 2017 12:02:00 +0000 Subject: pwr: Adds logic to enter power gating for the cpu model If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power Maintainer: Andreas Sandberg --- src/cpu/minor/cpu.cc | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'src/cpu/minor/cpu.cc') diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc index ae4fda6f6..68c07675f 100644 --- a/src/cpu/minor/cpu.cc +++ b/src/cpu/minor/cpu.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2014 ARM Limited + * Copyright (c) 2012-2014, 2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -195,6 +195,9 @@ MinorCPU::startup() DrainState MinorCPU::drain() { + // Deschedule any power gating event (if any) + deschedulePowerGatingEvent(); + if (switchedOut()) { DPRINTF(Drain, "Minor CPU switched out, draining not needed.\n"); return DrainState::Drained; @@ -240,10 +243,14 @@ MinorCPU::drainResume() "'timing' mode.\n"); } - for (ThreadID tid = 0; tid < numThreads; tid++) + for (ThreadID tid = 0; tid < numThreads; tid++){ wakeup(tid); + } pipeline->drainResume(); + + // Reschedule any power gating event (if any) + schedulePowerGatingEvent(); } void -- cgit v1.2.3