From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sun, 26 Jul 2015 10:21:20 -0500
Subject: cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.
---
 src/cpu/minor/dyn_inst.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/cpu/minor/dyn_inst.cc')

diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc
index ab08e6b4a..03cf785ef 100644
--- a/src/cpu/minor/dyn_inst.cc
+++ b/src/cpu/minor/dyn_inst.cc
@@ -157,6 +157,8 @@ printRegName(std::ostream &os, TheISA::RegIndex reg)
         break;
       case CCRegClass:
         os << 'c' << static_cast<unsigned int>(reg - TheISA::CC_Reg_Base);
+      case VectorRegClass:
+        os << 'v' << static_cast<unsigned int>(reg - TheISA::Vector_Reg_Base);
     }
 }
 
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