From 88bbabe93f339f9db301caf43bf2cca2a0e8048c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 19 Nov 2018 17:20:31 -0800 Subject: arch, cpu: Remove float type accessors. Use the binary accessors instead. Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2 Reviewed-on: https://gem5-review.googlesource.com/c/14457 Reviewed-by: Giacomo Travaglini Maintainer: Gabe Black --- src/cpu/minor/exec_context.hh | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) (limited to 'src/cpu/minor/exec_context.hh') diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 238d11352..19bae74bf 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -99,7 +99,7 @@ class ExecContext : public ::ExecContext setPredicate(true); thread.setIntReg(TheISA::ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread.setFloatReg(TheISA::ZeroReg, 0.0); + thread.setFloatRegBits(TheISA::ZeroReg, 0); #endif } @@ -129,14 +129,6 @@ class ExecContext : public ::ExecContext return thread.readIntReg(reg.index()); } - TheISA::FloatReg - readFloatRegOperand(const StaticInst *si, int idx) override - { - const RegId& reg = si->srcRegIdx(idx); - assert(reg.isFloatReg()); - return thread.readFloatReg(reg.index()); - } - TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override { @@ -177,15 +169,6 @@ class ExecContext : public ::ExecContext thread.setIntReg(reg.index(), val); } - void - setFloatRegOperand(const StaticInst *si, int idx, - TheISA::FloatReg val) override - { - const RegId& reg = si->destRegIdx(idx); - assert(reg.isFloatReg()); - thread.setFloatReg(reg.index(), val); - } - void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val) override -- cgit v1.2.3