From 25474167e5b247d1b91fbf802c5b396a63ae705e Mon Sep 17 00:00:00 2001 From: Giacomo Gabrielli Date: Tue, 16 Oct 2018 16:04:08 +0100 Subject: arch,cpu: Add vector predicate registers Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector Extension (SVE), introduce the notion of a predicate register file. This changeset adds this feature across architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/c/13715 Maintainer: Andreas Sandberg Reviewed-by: Jason Lowe-Power --- src/cpu/minor/exec_context.hh | 27 ++++++++++++++++++++++++++- src/cpu/minor/scoreboard.cc | 7 ++++++- src/cpu/minor/scoreboard.hh | 5 +++-- 3 files changed, 35 insertions(+), 4 deletions(-) (limited to 'src/cpu/minor') diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index b9ed3971f..4cb67372e 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2014, 2016 ARM Limited + * Copyright (c) 2011-2014, 2016-2017 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -161,6 +161,22 @@ class ExecContext : public ::ExecContext return thread.readVecElem(reg); } + const TheISA::VecPredRegContainer& + readVecPredRegOperand(const StaticInst *si, int idx) const override + { + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isVecPredReg()); + return thread.readVecPredReg(reg); + } + + TheISA::VecPredRegContainer& + getWritableVecPredRegOperand(const StaticInst *si, int idx) override + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecPredReg()); + return thread.getWritableVecPredReg(reg); + } + void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override { @@ -186,6 +202,15 @@ class ExecContext : public ::ExecContext thread.setVecReg(reg, val); } + void + setVecPredRegOperand(const StaticInst *si, int idx, + const TheISA::VecPredRegContainer& val) + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecPredReg()); + thread.setVecPredReg(reg, val); + } + /** Vector Register Lane Interfaces. */ /** @{ */ /** Reads source vector 8bit operand. */ diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc index 196d035eb..5c0e86a67 100644 --- a/src/cpu/minor/scoreboard.cc +++ b/src/cpu/minor/scoreboard.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, 2016 ARM Limited + * Copyright (c) 2013-2014, 2016-2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -77,6 +77,11 @@ Scoreboard::findIndex(const RegId& reg, Index &scoreboard_index) TheISA::NumFloatRegs + reg.flatIndex(); ret = true; break; + case VecPredRegClass: + scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs + + TheISA::NumFloatRegs + TheISA::NumVecRegs + reg.index(); + ret = true; + break; case CCRegClass: scoreboard_index = TheISA::NumIntRegs + reg.index(); ret = true; diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh index 37ae8da0a..b21e14e24 100644 --- a/src/cpu/minor/scoreboard.hh +++ b/src/cpu/minor/scoreboard.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, 2016 ARM Limited + * Copyright (c) 2013-2014, 2016-2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -95,7 +95,8 @@ class Scoreboard : public Named Named(name), numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs + TheISA::NumFloatRegs + - (TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg)), + (TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg) + + TheISA::NumVecPredRegs), numResults(numRegs, 0), numUnpredictableResults(numRegs, 0), fuIndices(numRegs, 0), -- cgit v1.2.3