From 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 19 Nov 2018 18:14:16 -0800 Subject: arch: cpu: Rename *FloatRegBits* to *FloatReg*. Now that there's no plain FloatReg, there's no reason to distinguish FloatRegBits with a special suffix since it's the only way to read or write FP registers. Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded Reviewed-on: https://gem5-review.googlesource.com/c/14460 Reviewed-by: Brandon Potter Reviewed-by: Giacomo Travaglini Maintainer: Gabe Black --- src/cpu/minor/exec_context.hh | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/cpu/minor') diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 4cb67372e..051cf412c 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -99,7 +99,7 @@ class ExecContext : public ::ExecContext setPredicate(true); thread.setIntReg(TheISA::ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread.setFloatRegBits(TheISA::ZeroReg, 0); + thread.setFloatReg(TheISA::ZeroReg, 0); #endif } @@ -134,7 +134,7 @@ class ExecContext : public ::ExecContext { const RegId& reg = si->srcRegIdx(idx); assert(reg.isFloatReg()); - return thread.readFloatRegBits(reg.index()); + return thread.readFloatReg(reg.index()); } const TheISA::VecRegContainer & @@ -190,7 +190,7 @@ class ExecContext : public ::ExecContext { const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); - thread.setFloatRegBits(reg.index(), val); + thread.setFloatReg(reg.index(), val); } void @@ -443,7 +443,7 @@ class ExecContext : public ::ExecContext return other_thread->readIntReg(reg.index()); break; case FloatRegClass: - return other_thread->readFloatRegBits(reg.index()); + return other_thread->readFloatReg(reg.index()); break; case MiscRegClass: return other_thread->readMiscReg(reg.index()); @@ -466,7 +466,7 @@ class ExecContext : public ::ExecContext return other_thread->setIntReg(reg.index(), val); break; case FloatRegClass: - return other_thread->setFloatRegBits(reg.index(), val); + return other_thread->setFloatReg(reg.index(), val); break; case MiscRegClass: return other_thread->setMiscReg(reg.index(), val); -- cgit v1.2.3