From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sun, 26 Jul 2015 10:21:20 -0500
Subject: cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.
---
 src/cpu/minor/dyn_inst.cc     |  2 ++
 src/cpu/minor/exec_context.hh | 43 +++++++++++++++++++++++++++++--------------
 src/cpu/minor/scoreboard.cc   |  8 ++++++++
 src/cpu/minor/scoreboard.hh   | 12 +++++++-----
 4 files changed, 46 insertions(+), 19 deletions(-)

(limited to 'src/cpu/minor')

diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc
index ab08e6b4a..03cf785ef 100644
--- a/src/cpu/minor/dyn_inst.cc
+++ b/src/cpu/minor/dyn_inst.cc
@@ -157,6 +157,8 @@ printRegName(std::ostream &os, TheISA::RegIndex reg)
         break;
       case CCRegClass:
         os << 'c' << static_cast<unsigned int>(reg - TheISA::CC_Reg_Base);
+      case VectorRegClass:
+        os << 'v' << static_cast<unsigned int>(reg - TheISA::Vector_Reg_Base);
     }
 }
 
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 80d5d9872..6ea74047c 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -140,6 +140,20 @@ class ExecContext : public ::ExecContext
         return thread.readFloatRegBits(reg_idx);
     }
 
+    TheISA::CCReg
+    readCCRegOperand(const StaticInst *si, int idx)
+    {
+        int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
+        return thread.readCCReg(reg_idx);
+    }
+
+    const TheISA::VectorReg &
+    readVectorRegOperand(const StaticInst *si, int idx)
+    {
+        int reg_idx = si->srcRegIdx(idx) - TheISA::Vector_Reg_Base;
+        return thread.readVectorReg(reg_idx);
+    }
+
     void
     setIntRegOperand(const StaticInst *si, int idx, IntReg val)
     {
@@ -162,6 +176,21 @@ class ExecContext : public ::ExecContext
         thread.setFloatRegBits(reg_idx, val);
     }
 
+    void
+    setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val)
+    {
+        int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
+        thread.setCCReg(reg_idx, val);
+    }
+
+    void
+    setVectorRegOperand(const StaticInst *si, int idx,
+                        const TheISA::VectorReg &val)
+    {
+        int reg_idx = si->destRegIdx(idx) - TheISA::Vector_Reg_Base;
+        thread.setVectorReg(reg_idx, val);
+    }
+
     bool
     readPredicate()
     {
@@ -265,20 +294,6 @@ class ExecContext : public ::ExecContext
         thread.getDTBPtr()->demapPage(vaddr, asn);
     }
 
-    TheISA::CCReg
-    readCCRegOperand(const StaticInst *si, int idx)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
-        return thread.readCCReg(reg_idx);
-    }
-
-    void
-    setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
-        thread.setCCReg(reg_idx, val);
-    }
-
     void
     demapInstPage(Addr vaddr, uint64_t asn)
     {
diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc
index f6b1f7944..3eb09271a 100644
--- a/src/cpu/minor/scoreboard.cc
+++ b/src/cpu/minor/scoreboard.cc
@@ -71,6 +71,11 @@ Scoreboard::findIndex(RegIndex reg, Index &scoreboard_index)
             scoreboard_index = TheISA::NumIntRegs + reg - TheISA::FP_Reg_Base;
             ret = true;
             break;
+          case VectorRegClass:
+            scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
+                    TheISA::NumFloatRegs + reg - TheISA::Vector_Reg_Base;
+            ret = true;
+            break;
           case MiscRegClass:
               /* Don't bother with Misc registers */
             ret = false;
@@ -99,6 +104,9 @@ flattenRegIndex(TheISA::RegIndex reg, ThreadContext *thread_context)
       case CCRegClass:
         ret = thread_context->flattenCCIndex(reg);
         break;
+      case VectorRegClass:
+        ret = thread_context->flattenVectorIndex(reg);
+        break;
       case MiscRegClass:
         /* Don't bother to flatten misc regs as we don't need them here */
         /* return thread_context->flattenMiscIndex(reg); */
diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh
index 711bcafb2..3a3a9d3c3 100644
--- a/src/cpu/minor/scoreboard.hh
+++ b/src/cpu/minor/scoreboard.hh
@@ -60,11 +60,13 @@ class Scoreboard : public Named
 {
   public:
     /** The number of registers in the Scoreboard.  These
-     *  are just the integer, CC and float registers packed
+     *  are just the integer, CC, float and vector registers packed
      *  together with integer regs in the range [0,NumIntRegs-1],
-     *  CC regs in the range [NumIntRegs, NumIntRegs+NumCCRegs-1]
-     *  and float regs in the range
-     *  [NumIntRegs+NumCCRegs, NumFloatRegs+NumIntRegs+NumCCRegs-1] */
+     *  CC regs in the range [NumIntRegs, NumIntRegs + NumCCRegs - 1],
+     *  float regs in the range
+     *  [NumIntRegs + NumCCRegs, NumFloatRegs + NumIntRegs + NumCCRegs - 1]
+     *  and vector regs in the range [NumFloatRegs + NumIntRegs + NumCCRegs,
+     *  NumFloatRegs + NumIntRegs + NumCCRegs + NumVectorRegs - 1]*/
     const unsigned numRegs;
 
     /** Type to use for thread context registers */
@@ -97,7 +99,7 @@ class Scoreboard : public Named
     Scoreboard(const std::string &name) :
         Named(name),
         numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs +
-            TheISA::NumFloatRegs),
+            TheISA::NumFloatRegs + TheISA::NumVectorRegs),
         numResults(numRegs, 0),
         numUnpredictableResults(numRegs, 0),
         fuIndices(numRegs, 0),
-- 
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