From b045de7e6969d5a40d4a3f9b178844cc911ac4c2 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 4 Jan 2019 16:20:49 +0000 Subject: cpu: Fix VecElemClass bugs in cpu models This patch is: * Adding a missing VecElemClass entry * Fixing assertion in rename map which was checking the number of free vector registers rather than free vector element registers * Fixing assertion in read/setVecElemOperand APIs. * Using the right register index in SimpleThread * Using VecElem instead of VecReg on O3 readArchVecElem Change-Id: I265320dcbe35eb47075991301dfc99333c5190c4 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/15598 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/cpu/minor/exec_context.hh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/minor') diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 76d46e905..b9ed3971f 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -157,7 +157,7 @@ class ExecContext : public ::ExecContext readVecElemOperand(const StaticInst *si, int idx) const override { const RegId& reg = si->srcRegIdx(idx); - assert(reg.isVecReg()); + assert(reg.isVecElem()); return thread.readVecElem(reg); } @@ -268,7 +268,7 @@ class ExecContext : public ::ExecContext const TheISA::VecElem val) override { const RegId& reg = si->destRegIdx(idx); - assert(reg.isVecReg()); + assert(reg.isVecElem()); thread.setVecElem(reg, val); } -- cgit v1.2.3