From fbdeb6031664d71e19a25f51b6ee882d803dac30 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Wed, 10 Feb 2016 04:08:24 -0500 Subject: mem: Deduce if cache should forward snoops This patch changes how the cache determines if snoops should be forwarded from the memory side to the CPU side. Instead of having a parameter, the cache now looks at the port connected on the CPU side, and if it is a snooping port, then snoops are forwarded. Less error prone, and less parameters to worry about. The patch also tidies up the CPU classes to ensure that their I-side port is not snooping by removing overrides to the snoop request handler, such that snoop requests will panic via the default MasterPort implement --- src/cpu/minor/cpu.hh | 3 --- src/cpu/minor/lsq.hh | 4 ++++ 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'src/cpu/minor') diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh index 82dac6aa9..dad015e89 100644 --- a/src/cpu/minor/cpu.hh +++ b/src/cpu/minor/cpu.hh @@ -107,9 +107,6 @@ class MinorCPU : public BaseCPU : MasterPort(name_, &cpu_), cpu(cpu_) { } - protected: - /** Snooping a coherence request, do nothing. */ - virtual void recvTimingSnoopReq(PacketPtr pkt) { } }; protected: diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh index 8a7d78216..33d7c506b 100644 --- a/src/cpu/minor/lsq.hh +++ b/src/cpu/minor/lsq.hh @@ -103,8 +103,12 @@ class LSQ : public Named void recvReqRetry() { lsq.recvReqRetry(); } + bool isSnooping() const override { return true; } + void recvTimingSnoopReq(PacketPtr pkt) { return lsq.recvTimingSnoopReq(pkt); } + + void recvFunctionalSnoop(PacketPtr pkt) { } }; DcachePort dcachePort; -- cgit v1.2.3