From 119f5f8e94e673b1495dccce03b54773dc18afea Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 1 Feb 2011 18:28:41 -0800 Subject: X86: Add L1 caches for the TLB walkers. Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly. --- src/cpu/o3/O3CPU.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/o3/O3CPU.py') diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 3f2210e44..38fee369c 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -141,7 +141,7 @@ class DerivO3CPU(BaseCPU): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") - def addPrivateSplitL1Caches(self, ic, dc): - BaseCPU.addPrivateSplitL1Caches(self, ic, dc) + def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): + BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc) self.icache.tgts_per_mshr = 20 self.dcache.tgts_per_mshr = 20 -- cgit v1.2.3