From 5c2fc35e029d8cd8e69e983e1baef6b86e47d64d Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Sat, 28 Jan 2012 19:09:04 -0600 Subject: O3 CPU LSQ: Implement TSO This patch makes O3's LSQ maintain total order between stores. Essentially only the store at the head of the store buffer is allowed to be in flight. Only after that store completes, the next store is issued to the memory system. By default, the x86 architecture will have TSO. --- src/cpu/o3/O3CPU.py | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/cpu/o3/O3CPU.py') diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 9dfcc8b9e..6f721a11b 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -143,3 +143,5 @@ class DerivO3CPU(BaseCPU): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") + needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', + "Enable TSO Memory model") -- cgit v1.2.3