From 537239b278f7b8171d2eb09ef7f99c332266c48f Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 26 Aug 2007 20:24:18 -0700
Subject: Address Translation: Make SE mode use an actual TLB/MMU for
 translation like FS.

--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
---
 src/cpu/o3/O3CPU.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/cpu/o3/O3CPU.py')

diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index e691cfe5d..27ca8ce1e 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -52,8 +52,8 @@ class DerivO3CPU(BaseCPU):
         else:
             checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
                                               warnOnlyOnLoadError=False), "checker")
-            checker.itb = Parent.itb
-            checker.dtb = Parent.dtb
+        checker.itb = Parent.itb
+        checker.dtb = Parent.dtb
 
     cachePorts = Param.Unsigned(200, "Cache Ports")
     icache_port = Port("Instruction Port")
-- 
cgit v1.2.3