From 12e26c68c3e12a17c29b694012819bc7bae7bb5a Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Sun, 12 Nov 2006 20:15:30 -0500
Subject: Updates to support new interrupt processing and removal of PcPAL.

src/arch/alpha/interrupts.hh:
    No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
    Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
    Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
    Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
    Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
    Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
    Fix broken if statement from PcPAL updates, and properly populate the request fields.

    Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
    Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
    Populate request fields properly.
src/cpu/simple/base.cc:
    Update for interrupt stuff.

--HG--
extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
---
 src/cpu/o3/alpha/cpu.hh      |  7 +++++--
 src/cpu/o3/alpha/cpu_impl.hh | 22 ++++++++++++++--------
 2 files changed, 19 insertions(+), 10 deletions(-)

(limited to 'src/cpu/o3/alpha')

diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index b62550062..0078db69f 100644
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -156,8 +156,11 @@ class AlphaO3CPU : public FullO3CPU<Impl>
 
     bool simPalCheck(int palFunc, unsigned tid);
 
-    /** Processes any interrupts. */
-    void processInterrupts();
+    /** Returns the Fault for any valid interrupt. */
+    Fault getInterrupts();
+
+    /** Processes any an interrupt fault. */
+    void processInterrupts(Fault interrupt);
 
     /** Halts the CPU. */
     void halt() { panic("Halt not implemented!\n"); }
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 04eadfa5a..f5c394826 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -266,9 +266,17 @@ AlphaO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
     return true;
 }
 
+template <class Impl>
+Fault
+AlphaO3CPU<Impl>::getInterrupts()
+{
+    // Check if there are any outstanding interrupts
+    return this->interrupts.getInterrupt(this->threadContexts[0]);
+}
+
 template <class Impl>
 void
-AlphaO3CPU<Impl>::processInterrupts()
+AlphaO3CPU<Impl>::processInterrupts(Fault interrupt)
 {
     // Check for interrupts here.  For now can copy the code that
     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
@@ -276,14 +284,12 @@ AlphaO3CPU<Impl>::processInterrupts()
     // @todo: Possibly consolidate the interrupt checking code.
     // @todo: Allow other threads to handle interrupts.
 
-    // Check if there are any outstanding interrupts
-    //Handle the interrupts
-    Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0));
+    assert(interrupt != NoFault);
+    this->interrupts.updateIntrInfo(this->threadContexts[0]);
 
-    if (interrupt != NoFault) {
-        this->checkInterrupts = false;
-        this->trap(interrupt, 0);
-    }
+    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
+    this->checkInterrupts = false;
+    this->trap(interrupt, 0);
 }
 
 #endif // FULL_SYSTEM
-- 
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