From 038217049a952a67f29b79c416a35d89fea31f70 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 03:37:01 -0500 Subject: Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions. --HG-- extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9 --- src/cpu/o3/alpha/cpu.hh | 4 ---- src/cpu/o3/alpha/cpu_impl.hh | 14 -------------- src/cpu/o3/alpha/dyn_inst_impl.hh | 14 -------------- 3 files changed, 32 deletions(-) (limited to 'src/cpu/o3/alpha') diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 9d97f9701..474fce02a 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -145,10 +145,6 @@ class AlphaO3CPU : public FullO3CPU #if FULL_SYSTEM /** Posts an interrupt. */ void post_interrupt(int int_num, int index); - /** Reads the interrupt flag. */ - int readIntrFlag(); - /** Sets the interrupt flags. */ - void setIntrFlag(int val); /** HW return from error interrupt. */ Fault hwrei(unsigned tid); /** Returns if a specific PC is a PAL mode PC. */ diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index b7362fad9..a57c5d9ed 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -241,20 +241,6 @@ AlphaO3CPU::post_interrupt(int int_num, int index) } } -template -int -AlphaO3CPU::readIntrFlag() -{ - return this->regFile.readIntrFlag(); -} - -template -void -AlphaO3CPU::setIntrFlag(int val) -{ - this->regFile.setIntrFlag(val); -} - template Fault AlphaO3CPU::hwrei(unsigned tid) diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh index b273a7b9b..f27cd5961 100644 --- a/src/cpu/o3/alpha/dyn_inst_impl.hh +++ b/src/cpu/o3/alpha/dyn_inst_impl.hh @@ -127,20 +127,6 @@ AlphaDynInst::hwrei() return NoFault; } -template -int -AlphaDynInst::readIntrFlag() -{ - return this->cpu->readIntrFlag(); -} - -template -void -AlphaDynInst::setIntrFlag(int val) -{ - this->cpu->setIntrFlag(val); -} - template bool AlphaDynInst::inPalMode() -- cgit v1.2.3 From 3c19c5f0f239b8d31a3a8acd03eff9923f19b6ee Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 04:12:52 -0500 Subject: Missed a few instances of this function. --HG-- extra : convert_revision : 581f97dafc2b30bd5067f6ff7f9cdbabc6890622 --- src/cpu/o3/alpha/dyn_inst.hh | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/cpu/o3/alpha') diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index 294aadde8..31a6f7753 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -127,10 +127,6 @@ class AlphaDynInst : public BaseDynInst #if FULL_SYSTEM /** Calls hardware return from error interrupt. */ Fault hwrei(); - /** Reads interrupt flag. */ - int readIntrFlag(); - /** Sets interrupt flag. */ - void setIntrFlag(int val); /** Checks if system is in PAL mode. */ bool inPalMode(); /** Traps to handle specified fault. */ -- cgit v1.2.3 From bfd5eb2b08dad700d085a637d5e16a61dcc530d7 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 31 Oct 2006 14:33:56 -0500 Subject: Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. configs/example/fs.py: configs/example/se.py: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.cc: src/cpu/thread_state.hh: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-atomic.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: No need for mem parameter any more. src/cpu/checker/cpu.cc: Use new constructor for simple thread (no more MemObject parameter). src/cpu/checker/cpu.hh: Remove MemObject parameter. src/cpu/memtest/memtest.hh: Ports now take in their MemObject owner. src/cpu/o3/alpha/cpu_builder.cc: Remove mem parameter. src/cpu/o3/alpha/cpu_impl.hh: Remove memory parameter and clean up handling of TranslatingPort. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/params.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/atomic.cc: Remove memory parameter. --HG-- extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3 --- src/cpu/o3/alpha/cpu_builder.cc | 6 ------ src/cpu/o3/alpha/cpu_impl.hh | 18 ++---------------- 2 files changed, 2 insertions(+), 22 deletions(-) (limited to 'src/cpu/o3/alpha') diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index ff123a6f7..ca316433b 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -61,8 +61,6 @@ Param profile; SimObjectVectorParam workload; #endif // FULL_SYSTEM -SimObjectParam mem; - SimObjectParam checker; Param max_insts_any_thread; @@ -169,8 +167,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) INIT_PARAM(workload, "Processes to run"), #endif // FULL_SYSTEM - INIT_PARAM(mem, "Memory"), - INIT_PARAM_DFLT(checker, "Checker CPU", NULL), INIT_PARAM_DFLT(max_insts_any_thread, @@ -314,8 +310,6 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->workload = workload; #endif // FULL_SYSTEM - params->mem = mem; - params->checker = checker; params->max_insts_any_thread = max_insts_any_thread; diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index b7362fad9..5deee27de 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -77,24 +77,10 @@ AlphaO3CPU::AlphaO3CPU(Params *params) if (i < params->workload.size()) { DPRINTF(O3CPU, "Workload[%i] process is %#x", i, this->thread[i]); - this->thread[i] = new Thread(this, i, params->workload[i], - i, params->mem); + this->thread[i] = new Thread(this, i, params->workload[i], i); this->thread[i]->setStatus(ThreadContext::Suspended); -#if !FULL_SYSTEM - /* Use this port to for syscall emulation writes to memory. */ - Port *mem_port; - TranslatingPort *trans_port; - trans_port = new TranslatingPort(csprintf("%s-%d-funcport", - name(), i), - params->workload[i]->pTable, - false); - mem_port = params->mem->getPort("functional"); - mem_port->setPeer(trans_port); - trans_port->setPeer(mem_port); - this->thread[i]->setMemPort(trans_port); -#endif //usedTids[i] = true; //threadMap[i] = i; } else { @@ -102,7 +88,7 @@ AlphaO3CPU::AlphaO3CPU(Params *params) //when scheduling threads to CPU Process* dummy_proc = NULL; - this->thread[i] = new Thread(this, i, dummy_proc, i, params->mem); + this->thread[i] = new Thread(this, i, dummy_proc, i); //usedTids[i] = false; } #endif // !FULL_SYSTEM -- cgit v1.2.3 From 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 1 Nov 2006 16:44:45 -0500 Subject: Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults --HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675 --- src/cpu/o3/alpha/cpu.hh | 16 +++++++++++----- src/cpu/o3/alpha/cpu_builder.cc | 4 ++-- src/cpu/o3/alpha/cpu_impl.hh | 13 ++++++------- src/cpu/o3/alpha/dyn_inst.hh | 9 ++++----- src/cpu/o3/alpha/params.hh | 11 +++++++---- src/cpu/o3/alpha/thread_context.hh | 4 ++-- 6 files changed, 32 insertions(+), 25 deletions(-) (limited to 'src/cpu/o3/alpha') diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 474fce02a..01749a2a2 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -37,6 +37,12 @@ #include "cpu/o3/cpu.hh" #include "sim/byteswap.hh" +namespace TheISA +{ + class ITB; + class DTB; +} + class EndQuiesceEvent; namespace Kernel { class Statistics; @@ -73,9 +79,9 @@ class AlphaO3CPU : public FullO3CPU #if FULL_SYSTEM /** ITB pointer. */ - AlphaITB *itb; + AlphaISA::ITB *itb; /** DTB pointer. */ - AlphaDTB *dtb; + AlphaISA::DTB *dtb; #endif /** Registers statistics. */ @@ -126,15 +132,15 @@ class AlphaO3CPU : public FullO3CPU /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid); + MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid); /** Sets a miscellaneous register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid); + void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid); + void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given * thread. The source of the squash is an external update of diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index ff123a6f7..a00dd5005 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -54,8 +54,8 @@ Param activity; #if FULL_SYSTEM SimObjectParam system; Param cpu_id; -SimObjectParam itb; -SimObjectParam dtb; +SimObjectParam itb; +SimObjectParam dtb; Param profile; #else SimObjectVectorParam workload; diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index a57c5d9ed..7f10e43c2 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -198,25 +198,24 @@ AlphaO3CPU::readMiscReg(int misc_reg, unsigned tid) template TheISA::MiscReg -AlphaO3CPU::readMiscRegWithEffect(int misc_reg, Fault &fault, - unsigned tid) +AlphaO3CPU::readMiscRegWithEffect(int misc_reg, unsigned tid) { - return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid); + return this->regFile.readMiscRegWithEffect(misc_reg, tid); } template -Fault +void AlphaO3CPU::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscReg(misc_reg, val, tid); + this->regFile.setMiscReg(misc_reg, val, tid); } template -Fault +void AlphaO3CPU::setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscRegWithEffect(misc_reg, val, tid); + this->regFile.setMiscRegWithEffect(misc_reg, val, tid); } template diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index 31a6f7753..e711de510 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -102,14 +102,13 @@ class AlphaDynInst : public BaseDynInst /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { - return this->cpu->readMiscRegWithEffect(misc_reg, fault, - this->threadNumber); + return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber); } /** Sets a misc. register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { this->instResult.integer = val; return this->cpu->setMiscReg(misc_reg, val, this->threadNumber); @@ -118,7 +117,7 @@ class AlphaDynInst : public BaseDynInst /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { return this->cpu->setMiscRegWithEffect(misc_reg, val, this->threadNumber); diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh index c618cee08..b6b84b2a1 100644 --- a/src/cpu/o3/alpha/params.hh +++ b/src/cpu/o3/alpha/params.hh @@ -35,8 +35,11 @@ #include "cpu/o3/params.hh" //Forward declarations -class AlphaDTB; -class AlphaITB; +namespace AlphaISA +{ + class DTB; + class ITB; +} class MemObject; class Process; class System; @@ -52,8 +55,8 @@ class AlphaSimpleParams : public O3Params public: #if FULL_SYSTEM - AlphaITB *itb; - AlphaDTB *dtb; + AlphaISA::ITB *itb; + AlphaISA::DTB *dtb; #endif }; diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh index 70a09940f..f0cecee35 100644 --- a/src/cpu/o3/alpha/thread_context.hh +++ b/src/cpu/o3/alpha/thread_context.hh @@ -37,10 +37,10 @@ class AlphaTC : public O3ThreadContext public: #if FULL_SYSTEM /** Returns a pointer to the ITB. */ - virtual AlphaITB *getITBPtr() { return this->cpu->itb; } + virtual AlphaISA::ITB *getITBPtr() { return this->cpu->itb; } /** Returns a pointer to the DTB. */ - virtual AlphaDTB *getDTBPtr() { return this->cpu->dtb; } + virtual AlphaISA::DTB *getDTBPtr() { return this->cpu->dtb; } /** Returns pointer to the quiesce event. */ virtual EndQuiesceEvent *getQuiesceEvent() -- cgit v1.2.3 From c8fc116c7636893517254f785707eba1726d3265 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 02:25:39 -0500 Subject: Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the --HG-- extra : convert_revision : c535000a6a170caefd441687b60f940513d29739 --- src/cpu/o3/alpha/cpu_impl.hh | 48 +++----------------------------------------- 1 file changed, 3 insertions(+), 45 deletions(-) (limited to 'src/cpu/o3/alpha') diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index f5c2170ce..170a53c23 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -270,7 +270,6 @@ template void AlphaO3CPU::processInterrupts() { - using namespace TheISA; // Check for interrupts here. For now can copy the code that // exists within isa_fullsys_traits.hh. Also assume that thread 0 // is the one that handles the interrupts. @@ -279,52 +278,11 @@ AlphaO3CPU::processInterrupts() // Check if there are any outstanding interrupts //Handle the interrupts - int ipl = 0; - int summary = 0; - this->checkInterrupts = false; + Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0)); - if (this->readMiscReg(IPR_ASTRR, 0)) - panic("asynchronous traps not implemented\n"); - - if (this->readMiscReg(IPR_SIRR, 0)) { - for (int i = INTLEVEL_SOFTWARE_MIN; - i < INTLEVEL_SOFTWARE_MAX; i++) { - if (this->readMiscReg(IPR_SIRR, 0) & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; - summary |= (ULL(1) << i); - } - } - } - - uint64_t interrupts = this->intr_status(); - - if (interrupts) { - for (int i = INTLEVEL_EXTERNAL_MIN; - i < INTLEVEL_EXTERNAL_MAX; i++) { - if (interrupts & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = i; - summary |= (ULL(1) << i); - } - } - } - - if (ipl && ipl > this->readMiscReg(IPR_IPLR, 0)) { - this->setMiscReg(IPR_ISR, summary, 0); - this->setMiscReg(IPR_INTID, ipl, 0); - // Checker needs to know these two registers were updated. -#if USE_CHECKER - if (this->checker) { - this->checker->threadBase()->setMiscReg(IPR_ISR, summary); - this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); - } -#endif - this->trap(Fault(new InterruptFault), 0); - DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - this->readMiscReg(IPR_IPLR, 0), ipl, summary); - } + if (interrupt != NoFault) + this->trap(interrupt, 0); } #endif // FULL_SYSTEM -- cgit v1.2.3 From 118b9dc1f9e84a12ea26743f6cec1eac5b4ab13a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 04:25:33 -0500 Subject: Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however. --HG-- extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b --- src/cpu/o3/alpha/cpu.hh | 3 --- src/cpu/o3/alpha/cpu_impl.hh | 5 +++-- src/cpu/o3/alpha/dyn_inst.hh | 2 -- src/cpu/o3/alpha/dyn_inst_impl.hh | 9 +-------- src/cpu/o3/alpha/thread_context.hh | 5 ----- 5 files changed, 4 insertions(+), 20 deletions(-) (limited to 'src/cpu/o3/alpha') diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 01749a2a2..b62550062 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -153,9 +153,6 @@ class AlphaO3CPU : public FullO3CPU void post_interrupt(int int_num, int index); /** HW return from error interrupt. */ Fault hwrei(unsigned tid); - /** Returns if a specific PC is a PAL mode PC. */ - bool inPalMode(uint64_t PC) - { return AlphaISA::PcPAL(PC); } bool simPalCheck(int palFunc, unsigned tid); diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 170a53c23..750ccc912 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -278,11 +278,12 @@ AlphaO3CPU::processInterrupts() // Check if there are any outstanding interrupts //Handle the interrupts - this->checkInterrupts = false; Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0)); - if (interrupt != NoFault) + if (interrupt != NoFault) { + this->checkInterrupts = false; this->trap(interrupt, 0); + } } #endif // FULL_SYSTEM diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index e711de510..31df8ff78 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -126,8 +126,6 @@ class AlphaDynInst : public BaseDynInst #if FULL_SYSTEM /** Calls hardware return from error interrupt. */ Fault hwrei(); - /** Checks if system is in PAL mode. */ - bool inPalMode(); /** Traps to handle specified fault. */ void trap(Fault fault); bool simPalCheck(int palFunc); diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh index f27cd5961..6fc548a85 100644 --- a/src/cpu/o3/alpha/dyn_inst_impl.hh +++ b/src/cpu/o3/alpha/dyn_inst_impl.hh @@ -113,7 +113,7 @@ Fault AlphaDynInst::hwrei() { // Can only do a hwrei when in pal mode. - if (!this->cpu->inPalMode(this->readPC())) + if (!(this->readPC() & 0x3)) return new AlphaISA::UnimplementedOpcodeFault; // Set the next PC based on the value of the EXC_ADDR IPR. @@ -127,13 +127,6 @@ AlphaDynInst::hwrei() return NoFault; } -template -bool -AlphaDynInst::inPalMode() -{ - return this->cpu->inPalMode(this->PC); -} - template void AlphaDynInst::trap(Fault fault) diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh index f0cecee35..bcecb7087 100644 --- a/src/cpu/o3/alpha/thread_context.hh +++ b/src/cpu/o3/alpha/thread_context.hh @@ -47,11 +47,6 @@ class AlphaTC : public O3ThreadContext { return this->thread->quiesceEvent; } - - /** Returns if the thread is currently in PAL mode, based on - * the PC's value. */ - virtual bool inPalMode() - { return TheISA::PcPAL(this->cpu->readPC(this->thread->readTid())); } #endif virtual uint64_t readNextNPC() -- cgit v1.2.3 From c693c6ba9f9d641344db8a2a505484f5f8aa2645 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 22:34:34 -0500 Subject: Put kernel_stats back into arch. --HG-- rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966 --- src/cpu/o3/alpha/cpu_impl.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/o3/alpha') diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 750ccc912..04eadfa5a 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -48,8 +48,8 @@ #if FULL_SYSTEM #include "arch/alpha/osfpal.hh" #include "arch/isa_traits.hh" +#include "arch/kernel_stats.hh" #include "cpu/quiesce_event.hh" -#include "kern/kernel_stats.hh" #include "sim/sim_exit.hh" #include "sim/system.hh" #endif -- cgit v1.2.3