From baba18ab9214d1fe2236cd932c3bfca5ddfb06d6 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 16 Jun 2006 17:08:47 -0400 Subject: Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble. First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model. Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled. SConstruct: Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled. configs/test/test.py: Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick. src/base/traceflags.py: Add in O3CPU trace flag. src/cpu/SConscript: Rename AlphaFullCPU to AlphaO3CPU. Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included. src/cpu/base_dyn_inst.cc: src/cpu/base_dyn_inst.hh: Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU. src/cpu/cpu_models.py: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_cpu_impl.hh: Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model. src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/commit.hh: src/cpu/o3/cpu.hh: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/thread_state.hh: src/python/m5/objects/AlphaO3CPU.py: Rename FullCPU to O3CPU to differentiate from old FullCPU model. src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: Rename FullCPU to O3CPU to differentiate from old FullCPU model. Also #ifdef the checker code so it doesn't need to be included if it's not selected. --HG-- rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a --- src/cpu/o3/alpha_cpu_impl.hh | 140 ++++++++++++++++++++++--------------------- 1 file changed, 73 insertions(+), 67 deletions(-) (limited to 'src/cpu/o3/alpha_cpu_impl.hh') diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh index bfd05d260..532611fb6 100644 --- a/src/cpu/o3/alpha_cpu_impl.hh +++ b/src/cpu/o3/alpha_cpu_impl.hh @@ -28,6 +28,8 @@ * Authors: Kevin Lim */ +#include "config/use_checker.hh" + #include "arch/alpha/faults.hh" #include "base/cprintf.hh" #include "base/statistics.hh" @@ -53,14 +55,14 @@ using namespace TheISA; template -AlphaFullCPU::AlphaFullCPU(Params *params) +AlphaO3CPU::AlphaO3CPU(Params *params) #if FULL_SYSTEM : FullO3CPU(params), itb(params->itb), dtb(params->dtb) #else : FullO3CPU(params) #endif { - DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n"); + DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n"); // Setup any thread state. this->thread.resize(this->numThreads); @@ -73,7 +75,7 @@ AlphaFullCPU::AlphaFullCPU(Params *params) this->thread[i]->setStatus(ThreadContext::Suspended); #else if (i < params->workload.size()) { - DPRINTF(FullCPU, "FullCPU: Workload[%i] process is %#x", + DPRINTF(O3CPU, "Workload[%i] process is %#x", i, this->thread[i]); this->thread[i] = new Thread(this, i, params->workload[i], i, params->mem); @@ -110,14 +112,16 @@ AlphaFullCPU::AlphaFullCPU(Params *params) // Setup the TC that will serve as the interface to the threads/CPU. AlphaTC *alpha_tc = new AlphaTC; + tc = alpha_tc; + // If we're using a checker, then the TC should be the // CheckerThreadContext. +#if USE_CHECKER if (params->checker) { tc = new CheckerThreadContext( alpha_tc, this->checker); - } else { - tc = alpha_tc; } +#endif alpha_tc->cpu = this; alpha_tc->thread = this->thread[i]; @@ -172,7 +176,7 @@ AlphaFullCPU::AlphaFullCPU(Params *params) template void -AlphaFullCPU::regStats() +AlphaO3CPU::regStats() { // Register stats for everything that has stats. this->fullCPURegStats(); @@ -186,7 +190,7 @@ AlphaFullCPU::regStats() #if FULL_SYSTEM template VirtualPort * -AlphaFullCPU::AlphaTC::getVirtPort(ThreadContext *src_tc) +AlphaO3CPU::AlphaTC::getVirtPort(ThreadContext *src_tc) { if (!src_tc) return thread->getVirtPort(); @@ -203,7 +207,7 @@ AlphaFullCPU::AlphaTC::getVirtPort(ThreadContext *src_tc) template void -AlphaFullCPU::AlphaTC::dumpFuncProfile() +AlphaO3CPU::AlphaTC::dumpFuncProfile() { // Currently not supported } @@ -211,7 +215,7 @@ AlphaFullCPU::AlphaTC::dumpFuncProfile() template void -AlphaFullCPU::AlphaTC::takeOverFrom(ThreadContext *old_context) +AlphaO3CPU::AlphaTC::takeOverFrom(ThreadContext *old_context) { // some things should already be set up #if FULL_SYSTEM @@ -253,7 +257,7 @@ AlphaFullCPU::AlphaTC::takeOverFrom(ThreadContext *old_context) #if FULL_SYSTEM template void -AlphaFullCPU::AlphaTC::delVirtPort(VirtualPort *vp) +AlphaO3CPU::AlphaTC::delVirtPort(VirtualPort *vp) { delete vp->getPeer(); delete vp; @@ -262,9 +266,9 @@ AlphaFullCPU::AlphaTC::delVirtPort(VirtualPort *vp) template void -AlphaFullCPU::AlphaTC::activate(int delay) +AlphaO3CPU::AlphaTC::activate(int delay) { - DPRINTF(FullCPU, "Calling activate on AlphaTC\n"); + DPRINTF(O3CPU, "Calling activate on AlphaTC\n"); if (thread->status() == ThreadContext::Active) return; @@ -286,9 +290,9 @@ AlphaFullCPU::AlphaTC::activate(int delay) template void -AlphaFullCPU::AlphaTC::suspend() +AlphaO3CPU::AlphaTC::suspend() { - DPRINTF(FullCPU, "Calling suspend on AlphaTC\n"); + DPRINTF(O3CPU, "Calling suspend on AlphaTC\n"); if (thread->status() == ThreadContext::Suspended) return; @@ -312,9 +316,9 @@ AlphaFullCPU::AlphaTC::suspend() template void -AlphaFullCPU::AlphaTC::deallocate() +AlphaO3CPU::AlphaTC::deallocate() { - DPRINTF(FullCPU, "Calling deallocate on AlphaTC\n"); + DPRINTF(O3CPU, "Calling deallocate on AlphaTC\n"); if (thread->status() == ThreadContext::Unallocated) return; @@ -325,9 +329,9 @@ AlphaFullCPU::AlphaTC::deallocate() template void -AlphaFullCPU::AlphaTC::halt() +AlphaO3CPU::AlphaTC::halt() { - DPRINTF(FullCPU, "Calling halt on AlphaTC\n"); + DPRINTF(O3CPU, "Calling halt on AlphaTC\n"); if (thread->status() == ThreadContext::Halted) return; @@ -338,7 +342,7 @@ AlphaFullCPU::AlphaTC::halt() template void -AlphaFullCPU::AlphaTC::regStats(const std::string &name) +AlphaO3CPU::AlphaTC::regStats(const std::string &name) { #if FULL_SYSTEM thread->kernelStats = new Kernel::Statistics(cpu->system); @@ -348,7 +352,7 @@ AlphaFullCPU::AlphaTC::regStats(const std::string &name) template void -AlphaFullCPU::AlphaTC::serialize(std::ostream &os) +AlphaO3CPU::AlphaTC::serialize(std::ostream &os) { #if FULL_SYSTEM if (thread->kernelStats) @@ -359,7 +363,7 @@ AlphaFullCPU::AlphaTC::serialize(std::ostream &os) template void -AlphaFullCPU::AlphaTC::unserialize(Checkpoint *cp, const std::string §ion) +AlphaO3CPU::AlphaTC::unserialize(Checkpoint *cp, const std::string §ion) { #if FULL_SYSTEM if (thread->kernelStats) @@ -371,46 +375,46 @@ AlphaFullCPU::AlphaTC::unserialize(Checkpoint *cp, const std::string § #if FULL_SYSTEM template EndQuiesceEvent * -AlphaFullCPU::AlphaTC::getQuiesceEvent() +AlphaO3CPU::AlphaTC::getQuiesceEvent() { return thread->quiesceEvent; } template Tick -AlphaFullCPU::AlphaTC::readLastActivate() +AlphaO3CPU::AlphaTC::readLastActivate() { return thread->lastActivate; } template Tick -AlphaFullCPU::AlphaTC::readLastSuspend() +AlphaO3CPU::AlphaTC::readLastSuspend() { return thread->lastSuspend; } template void -AlphaFullCPU::AlphaTC::profileClear() +AlphaO3CPU::AlphaTC::profileClear() {} template void -AlphaFullCPU::AlphaTC::profileSample() +AlphaO3CPU::AlphaTC::profileSample() {} #endif template TheISA::MachInst -AlphaFullCPU::AlphaTC:: getInst() +AlphaO3CPU::AlphaTC:: getInst() { return thread->getInst(); } template void -AlphaFullCPU::AlphaTC::copyArchRegs(ThreadContext *tc) +AlphaO3CPU::AlphaTC::copyArchRegs(ThreadContext *tc) { // This function will mess things up unless the ROB is empty and // there are no instructions in the pipeline. @@ -421,7 +425,7 @@ AlphaFullCPU::AlphaTC::copyArchRegs(ThreadContext *tc) for (int i = 0; i < AlphaISA::NumIntRegs; ++i) { renamed_reg = cpu->renameMap[tid].lookup(i); - DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, " + DPRINTF(O3CPU, "Copying over register %i, had data %lli, " "now has data %lli.\n", renamed_reg, cpu->readIntReg(renamed_reg), tc->readIntReg(i)); @@ -449,19 +453,19 @@ AlphaFullCPU::AlphaTC::copyArchRegs(ThreadContext *tc) template void -AlphaFullCPU::AlphaTC::clearArchRegs() +AlphaO3CPU::AlphaTC::clearArchRegs() {} template uint64_t -AlphaFullCPU::AlphaTC::readIntReg(int reg_idx) +AlphaO3CPU::AlphaTC::readIntReg(int reg_idx) { return cpu->readArchIntReg(reg_idx, thread->readTid()); } template FloatReg -AlphaFullCPU::AlphaTC::readFloatReg(int reg_idx, int width) +AlphaO3CPU::AlphaTC::readFloatReg(int reg_idx, int width) { switch(width) { case 32: @@ -476,14 +480,14 @@ AlphaFullCPU::AlphaTC::readFloatReg(int reg_idx, int width) template FloatReg -AlphaFullCPU::AlphaTC::readFloatReg(int reg_idx) +AlphaO3CPU::AlphaTC::readFloatReg(int reg_idx) { return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); } template FloatRegBits -AlphaFullCPU::AlphaTC::readFloatRegBits(int reg_idx, int width) +AlphaO3CPU::AlphaTC::readFloatRegBits(int reg_idx, int width) { DPRINTF(Fault, "Reading floatint register through the TC!\n"); return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); @@ -491,14 +495,14 @@ AlphaFullCPU::AlphaTC::readFloatRegBits(int reg_idx, int width) template FloatRegBits -AlphaFullCPU::AlphaTC::readFloatRegBits(int reg_idx) +AlphaO3CPU::AlphaTC::readFloatRegBits(int reg_idx) { return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } template void -AlphaFullCPU::AlphaTC::setIntReg(int reg_idx, uint64_t val) +AlphaO3CPU::AlphaTC::setIntReg(int reg_idx, uint64_t val) { cpu->setArchIntReg(reg_idx, val, thread->readTid()); @@ -510,7 +514,7 @@ AlphaFullCPU::AlphaTC::setIntReg(int reg_idx, uint64_t val) template void -AlphaFullCPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width) +AlphaO3CPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width) { switch(width) { case 32: @@ -529,7 +533,7 @@ AlphaFullCPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width) template void -AlphaFullCPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val) +AlphaO3CPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val) { cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); @@ -540,7 +544,7 @@ AlphaFullCPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val) template void -AlphaFullCPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val, +AlphaO3CPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { DPRINTF(Fault, "Setting floatint register through the TC!\n"); @@ -554,7 +558,7 @@ AlphaFullCPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val, template void -AlphaFullCPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val) +AlphaO3CPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val) { cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); @@ -566,7 +570,7 @@ AlphaFullCPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val) template void -AlphaFullCPU::AlphaTC::setPC(uint64_t val) +AlphaO3CPU::AlphaTC::setPC(uint64_t val) { cpu->setPC(val, thread->readTid()); @@ -578,7 +582,7 @@ AlphaFullCPU::AlphaTC::setPC(uint64_t val) template void -AlphaFullCPU::AlphaTC::setNextPC(uint64_t val) +AlphaO3CPU::AlphaTC::setNextPC(uint64_t val) { cpu->setNextPC(val, thread->readTid()); @@ -590,7 +594,7 @@ AlphaFullCPU::AlphaTC::setNextPC(uint64_t val) template Fault -AlphaFullCPU::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val) +AlphaO3CPU::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val) { Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid()); @@ -604,8 +608,8 @@ AlphaFullCPU::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val) template Fault -AlphaFullCPU::AlphaTC::setMiscRegWithEffect(int misc_reg, - const MiscReg &val) +AlphaO3CPU::AlphaTC::setMiscRegWithEffect(int misc_reg, + const MiscReg &val) { Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid()); @@ -622,21 +626,21 @@ AlphaFullCPU::AlphaTC::setMiscRegWithEffect(int misc_reg, template TheISA::IntReg -AlphaFullCPU::AlphaTC::getSyscallArg(int i) +AlphaO3CPU::AlphaTC::getSyscallArg(int i) { return cpu->getSyscallArg(i, thread->readTid()); } template void -AlphaFullCPU::AlphaTC::setSyscallArg(int i, IntReg val) +AlphaO3CPU::AlphaTC::setSyscallArg(int i, IntReg val) { cpu->setSyscallArg(i, val, thread->readTid()); } template void -AlphaFullCPU::AlphaTC::setSyscallReturn(SyscallReturn return_value) +AlphaO3CPU::AlphaTC::setSyscallReturn(SyscallReturn return_value) { cpu->setSyscallReturn(return_value, thread->readTid()); } @@ -645,37 +649,37 @@ AlphaFullCPU::AlphaTC::setSyscallReturn(SyscallReturn return_value) template MiscReg -AlphaFullCPU::readMiscReg(int misc_reg, unsigned tid) +AlphaO3CPU::readMiscReg(int misc_reg, unsigned tid) { return this->regFile.readMiscReg(misc_reg, tid); } template MiscReg -AlphaFullCPU::readMiscRegWithEffect(int misc_reg, Fault &fault, - unsigned tid) +AlphaO3CPU::readMiscRegWithEffect(int misc_reg, Fault &fault, + unsigned tid) { return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid); } template Fault -AlphaFullCPU::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) +AlphaO3CPU::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) { return this->regFile.setMiscReg(misc_reg, val, tid); } template Fault -AlphaFullCPU::setMiscRegWithEffect(int misc_reg, const MiscReg &val, - unsigned tid) +AlphaO3CPU::setMiscRegWithEffect(int misc_reg, const MiscReg &val, + unsigned tid) { return this->regFile.setMiscRegWithEffect(misc_reg, val, tid); } template void -AlphaFullCPU::squashFromTC(unsigned tid) +AlphaO3CPU::squashFromTC(unsigned tid) { this->thread[tid]->inSyscall = true; this->commit.generateTCEvent(tid); @@ -685,7 +689,7 @@ AlphaFullCPU::squashFromTC(unsigned tid) template void -AlphaFullCPU::post_interrupt(int int_num, int index) +AlphaO3CPU::post_interrupt(int int_num, int index) { BaseCPU::post_interrupt(int_num, index); @@ -697,21 +701,21 @@ AlphaFullCPU::post_interrupt(int int_num, int index) template int -AlphaFullCPU::readIntrFlag() +AlphaO3CPU::readIntrFlag() { return this->regFile.readIntrFlag(); } template void -AlphaFullCPU::setIntrFlag(int val) +AlphaO3CPU::setIntrFlag(int val) { this->regFile.setIntrFlag(val); } template Fault -AlphaFullCPU::hwrei(unsigned tid) +AlphaO3CPU::hwrei(unsigned tid) { // Need to clear the lock flag upon returning from an interrupt. this->lockFlag = false; @@ -726,7 +730,7 @@ AlphaFullCPU::hwrei(unsigned tid) template bool -AlphaFullCPU::simPalCheck(int palFunc, unsigned tid) +AlphaO3CPU::simPalCheck(int palFunc, unsigned tid) { if (this->thread[tid]->kernelStats) this->thread[tid]->kernelStats->callpal(palFunc, @@ -751,7 +755,7 @@ AlphaFullCPU::simPalCheck(int palFunc, unsigned tid) template void -AlphaFullCPU::trap(Fault fault, unsigned tid) +AlphaO3CPU::trap(Fault fault, unsigned tid) { // Pass the thread's TC into the invoke method. fault->invoke(this->threadContexts[tid]); @@ -759,7 +763,7 @@ AlphaFullCPU::trap(Fault fault, unsigned tid) template void -AlphaFullCPU::processInterrupts() +AlphaO3CPU::processInterrupts() { // Check for interrupts here. For now can copy the code that // exists within isa_fullsys_traits.hh. Also assume that thread 0 @@ -805,10 +809,12 @@ AlphaFullCPU::processInterrupts() this->setMiscReg(IPR_ISR, summary, 0); this->setMiscReg(IPR_INTID, ipl, 0); // Checker needs to know these two registers were updated. +#if USE_CHECKER if (this->checker) { this->checker->threadBase()->setMiscReg(IPR_ISR, summary); this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); } +#endif this->trap(Fault(new InterruptFault), 0); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", this->readMiscReg(IPR_IPLR, 0), ipl, summary); @@ -821,9 +827,9 @@ AlphaFullCPU::processInterrupts() template void -AlphaFullCPU::syscall(int64_t callnum, int tid) +AlphaO3CPU::syscall(int64_t callnum, int tid) { - DPRINTF(FullCPU, "AlphaFullCPU: [tid:%i] Executing syscall().\n\n", tid); + DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); DPRINTF(Activity,"Activity: syscall() called.\n"); @@ -841,21 +847,21 @@ AlphaFullCPU::syscall(int64_t callnum, int tid) template TheISA::IntReg -AlphaFullCPU::getSyscallArg(int i, int tid) +AlphaO3CPU::getSyscallArg(int i, int tid) { return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid); } template void -AlphaFullCPU::setSyscallArg(int i, IntReg val, int tid) +AlphaO3CPU::setSyscallArg(int i, IntReg val, int tid) { this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid); } template void -AlphaFullCPU::setSyscallReturn(SyscallReturn return_value, int tid) +AlphaO3CPU::setSyscallReturn(SyscallReturn return_value, int tid) { // check for error condition. Alpha syscall convention is to // indicate success/failure in reg a3 (r19) and put the -- cgit v1.2.3