From 8ade33d324218737c815935120307153975eeadc Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Fri, 7 Jul 2006 17:33:24 -0400
Subject: Support Ron's changes for hooking up ports.

src/cpu/checker/cpu.hh:
    Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
    Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
    Add ports to the parameters.

--HG--
extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
---
 src/cpu/o3/cpu.cc | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/cpu/o3/cpu.cc')

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index ceba74ef3..a9a1a7c9b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -360,6 +360,18 @@ FullO3CPU<Impl>::fullCPURegStats()
 
 }
 
+template <class Impl>
+Port *
+FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
+{
+    if (if_name == "dcache_port")
+        return iew.getDcachePort();
+    else if (if_name == "icache_port")
+        return fetch.getIcachePort();
+    else
+        panic("No Such Port\n");
+}
+
 template <class Impl>
 void
 FullO3CPU<Impl>::tick()
-- 
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