From c3081d9c1c36e1a08c173048783d191fa19463de Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 14 Apr 2007 17:13:18 +0000
Subject: Add support for microcode and pull out the special branch delay slot
 handling. Branch delay slots need to be squash on a mispredict as well
 because the nnpc they saw was incorrect.

--HG--
extra : convert_revision : 8b9c603616bcad254417a7a3fa3edfb4c8728719
---
 src/cpu/o3/cpu.cc | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

(limited to 'src/cpu/o3/cpu.cc')

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b2b4645d2..59978a065 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -696,7 +696,7 @@ FullO3CPU<Impl>::removeThread(unsigned tid)
 
     // Squash Throughout Pipeline
     InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
-    fetch.squash(0, sizeof(TheISA::MachInst), squash_seq_num, tid);
+    fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid);
     decode.squash(tid);
     rename.squash(squash_seq_num, tid);
     iew.squash(tid);
@@ -1150,6 +1150,20 @@ FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
     commit.setPC(new_PC, tid);
 }
 
+template <class Impl>
+uint64_t
+FullO3CPU<Impl>::readMicroPC(unsigned tid)
+{
+    return commit.readMicroPC(tid);
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid)
+{
+    commit.setMicroPC(new_PC, tid);
+}
+
 template <class Impl>
 uint64_t
 FullO3CPU<Impl>::readNextPC(unsigned tid)
@@ -1178,6 +1192,20 @@ FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid)
     commit.setNextNPC(val, tid);
 }
 
+template <class Impl>
+uint64_t
+FullO3CPU<Impl>::readNextMicroPC(unsigned tid)
+{
+    return commit.readNextMicroPC(tid);
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid)
+{
+    commit.setNextMicroPC(new_PC, tid);
+}
+
 template <class Impl>
 typename FullO3CPU<Impl>::ListIt
 FullO3CPU<Impl>::addInst(DynInstPtr &inst)
-- 
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