From f76b874533045543e56a69c1b5d75b34fbc8a888 Mon Sep 17 00:00:00 2001
From: Iru Cai <mytbk920423@gmail.com>
Date: Wed, 3 Apr 2019 10:29:37 +0800
Subject: check loads using tainted registers, set USL dst as tainted

---
 src/cpu/o3/cpu.cc | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'src/cpu/o3/cpu.cc')

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2566cf12a..ad4e6d549 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1285,6 +1285,13 @@ FullO3CPU<Impl>::setTaint(PhysRegIdPtr phys_reg)
     regFile.setTaint(phys_reg);
 }
 
+template <class Impl>
+bool
+FullO3CPU<Impl>::regTainted(PhysRegIdPtr phys_reg)
+{
+    return regFile.regTainted(phys_reg);
+}
+
 template <class Impl>
 uint64_t
 FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
-- 
cgit v1.2.3